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1-2 under development specifications in this manual are tentative and subject to change rev. g description mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer description the M30222 single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 100-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high-level of instruction efficiency and are capable of executing instructions at high speed. they also feature a built-in multiplier and dmac, making them ideal for controlling office, communications, industrial equipment, and other high-speed pro- cessing applications. the M30222 group includes a range of products with various package types. features ? memory capacity ......................................... flash rom 260 kbytes ...................................................................... ram 20 kbytes ? shortest instruction execution time ............. 62.5ns (f(x in )=16mh z ) ? supply voltage ............................................ 2.7 to 5.5v ? low power consumption ............................. tbd ? interrupts ..................................................... 25 internal and 8 external interrupt sources 4 software interrupt sources 7 levels (including key input interrupt) ? multifunction 16-bit timer ............................. 5 output timers, 6 input timers, three phase motor control, real-time port ? serial i/o ..................................................... 5 channel 3 for uart or clock synchronous (1 channel for i 2 c or spi) 2 for clock synchronous ? dmac ........................................................... 2 channels (trigger: 24 sources) ? a-d converter ............................................... 10 bits x 8 channels (expandable up to 10 channels) ? d-a converter ............................................... 8 bits x 2 channels ? crc calculation circuit ................................. 1 circuit ? watchdog timer ............................................ 1 timer ? key-on wake up ........................................... 8 inputs ? programmable i/o ........................................ 54 lines ? input port ...................................................... 1 line (p8 3 shared with nmi pin) ? clock generating circuit ............................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) ?lcd drive ...................................................... 1/2, 1/3 bias 4 common outputs 40 segment outputs built-in charge pump 1/2, 1/3, 1/4 duty expansion clk output static/direct drive mode applications audio, cameras, office, industrial, communications and, portable equipment specifications written in this manual are believed to be accurate but are not guaranteed to be entirely error free. they may be changed for func- tional or performance improvements. please make sure your manual is the latest version.
1-3 under development mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer specifications in this manual are tentative and subject to change rev. g description table of contents description ............................................................ 1-2 operation of functional blocks ............................ 1-10 memory ............................................................... 1-10 central processing unit (cpu) ............................ 1-11 reset ................................................................... 1-14 special function registers ..................................... 1-15 software reset .................................................... 1-20 clock generating circuit ...................................... 1-21 clock output ........................................................ 1-25 wait mode ........................................................... 1-26 stop mode ........................................................... 1-27 status transition of bclk ................................... 1-28 voltage down converter ...................................... 1-30 power control....................................................... 1-32 protection ............................................................ 1-34 software wait ....................................................... 1-35 overview of interrupts .......................................... 1-36 watchdog timer .................................................. 1-57 dmac .................................................................. 1-59 timers ................................................................. 1-69 timer a ................................................................ 1-71 timer b ................................................................ 1-85 timer functions for three-phase motor control ..... 1-93 serial communications ...................................... 1-105 (1) clock synchronous serial i/o mode .............. 1-114 (2) clock asynchronous serial i/o (uart) mode1-120 uart2 in i2c mode .......................................... 1-130 uart2 in spi mode .......................................... 1-138 s i/o 3, 4 ........................................................... 1-143 lcd drive control circuit .................................. 1-147 a-d converter ................................................... 1-157 d-a converter .................................................... 1-168 crc calculation circuit ..................................... 1-170 programmable i/o ports .................................... 1-172 electrical characteristics ................................... 1-179 flash memory .................................................... 1-186 cpu rewrite mode ............................................ 1-188 parallel i/o mode ............................................... 1-202 standard serial i/o mode 1 ................................ 1-206 standard serial i/o mode 2 ................................ 1-226
1-4 under development specifications in this manual are tentative and subject to change rev. g description mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer pin configuration figure 1.1 shows the pin configurations for M30222 group. fig. 1.1. pin configuration (top view) 91 85 86 87 88 89 90 92 93 94 95 96 97 98 99 81 82 83 84 100 40 2 1 seg30/p36 vl3 p74/ta2out/w 46 24 vl1 com2 p107/an7/int7 p106/an6/int6 p105/an5 p104/an4 p103/an3 p102/an2 p101/an1 avss p100/an0 vref avcc p97/adtrg/led7/sin4/int3 p75/ta2in/w 23 p76/ta3out/int4 22 p77/ta3in/int4 21 p80/ta4out/int5 /u 20 p82/int0 19 p81/ta4in/int5 /u 18 p83/nmi 17 v cc 16 xin 15 vss 14 xout 13 reset 12 11 p85/xcin 10 cnvss 9 p86/ int1 8 p90/tb0in/ int2 /clk3 7 p91/tb1in/sin3 6 p92/tb2in/sout3 5 p93/da0/tb3in 4 p94/da1/tb4in 3 p95/anex0/clk4 p96/anex1/sout4 seg31/p37 45 seg32/p40 44 seg33/p41 43 seg34/p42 42 seg35/p43 41 seg36/p44 seg37/p45 39 38 37 p60/cts0 /rts0 /ki0 36 p61/clk0/ki1 35 p62/rxd0/ki2 34 p63/txd0/ki3 33 p64/cts1 /rts1 /cts0 /clks1/ki4 32 p65/clk1/ki5 M30222fg p67/txd1/ki7 29 p70/txd2/sda/ta0out 28 p71/rxd2/scl/ta0in/tb5in 27 p72/clk2/ta1out/v 26 p73/cts2 /rts2 /ta1in/v 25 p66/rxd1/ki6 30 seg26/p32 50 seg27/p33 49 seg28/p34 48 seg29/p35 47 com1 com0 c2 c1 p84/xcout seg38/p46/rtp0 seg39/p47/rtp1 vl2 79 80 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 52 53 54 55 56 51 31 seg19 seg18 seg17 seg16 seg15 vcc seg14 vss seg13 seg12 seg11 seg10 seg09 seg08 seg07 seg06 seg05 seg04 seg03 seg02 seg01 seg00 com3 seg25/p31 seg24/p30 seg23 seg22 seg21 seg20 vdc
1-5 under development mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer specifications in this manual are tentative and subject to change rev. g description block diagram figure 1.2 is a block diagram of the M30222 group. fig. 1.2. block diagram of M30222 group timer timer ta0 (16 bits) timer ta1 (16 bits) timer ta2 (16 bits) timer ta3 (16 bits) timer ta4 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tb2 (16 bits) timer tb3 (16 bits) timer tb4 (16 bits) timer tb5 (16 bits) internal peripheral functions watchdog timer (15 bits) dmac (2 channels) d-a converter (8 bits x 2 channels) a-d converter (10 bits x 8 channels expandable up to 10 channels) uart/clock synchronous si/o (8 bits x 3 channels) system clock generator x in -x out x cin -x cout m16c/60 series16-bit cpu core i/o ports com 0-3 4 seg 0-23 24 port p3 seg 24-31 8 port p4 seg 32-39 8 port p6 8 r0l r0h r1h r1l r2 r3 a0 a1 fb r0l r0h r1h r1l r2 r3 a0 a1 fb registers isp usp stack pointer vector table intb crc arithmetic circuit (ccitt ) (polynomial : x 16 +x 12 +x 5 +1) multiplier port p10 port p9 port p8 port p7 memory port p8 3 rom (note 1) ram (note 2) note 1: rom size depends on mcu type. note 2: ram size depends on mcu type. sb flg pc program counter clock synchronous si/o (8 bits x 2 channels) vdc lcd controller 8 8 8 1 6 memory expansion figure 1.3 shows the memory expansion for the M30222 group. fig. 1.3. memory expansion M30222fc/fp/gp rom size (bytes) 260k 128k 96k 64k 32k 20k sram flash memory version
1-6 under development specifications in this manual are tentative and subject to change rev. g description mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer performance outline table 1.1. performance outline of the M30222 group parameters functions number of basic instructions 91 shortest instruction execution time 62.5ns f(xin) = 16mhz memory size rom 260k bytes ram 20k bytes input/output p3-p4, p6-p10 except p83 i/o 8 bits x 6, 7 bits x 1 p83 i 1 bit x 1 multifunctional timer ta0, ta1, ta2, ta3, ta4 16 bits x 5 tb0, tb1, tb2, tb3, tb4, tb5 16 bits x 6, three-phase motor control serial i/o uart0, uart1, uart2 (uart or clock synchronous) x 3, or i 2 c x 1 sio3, sio4 (clock synchronous) x 2 a-d converter 10 bits x (8 + 2) channels d-a converter 8 bits x 2 crc calculation circuit crc-ccitt watchdog timer 15 bits x 1 (with prescaler) interrupts 25 external, 8 internal sources, 4 software, 7 levels clock generating circuit 2 built-in clock generation circuits supply voltage 2.7 to 5.5v f(xin) = 16 mhz, without software wait power consumption tbd i/o characteristics i/o withstand voltage 5.5v output current p3, p4 0.1 ma (high output), 2.5 ma (low output) p6-p10 5 ma at 5v (excluding pins p7 0 , p7 1 , p8 3 ) device configuration cmos high performance silicon gate package 100-pin plastic mold qfp lcd com0 to com3 4 lines seg0 to seg39 40 lines (16 lines shared with i/o ports)
1-7 under development mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer specifications in this manual are tentative and subject to change rev. g description mitsubishi plans to release the following products in the M30222 group: (1) support for flash memory version and mask rom versions (2) rom capacity: 260 k bytes (3) package 100p6s-a : plastic molded qfp (mask rom version) 100p6q-a: plastic molded qfp fig. 1.4. type no., memory size, and package m16c family group figure 1.4 shows the M30222 family. package type: fp: package 100p6s-a gp: 100p6q-a rom no. omitted for flash memory version rom capacity: g: 260k bytes memory type: f : flash memory version type no. m 3 0 2 2 2 f g ? x x x f p M30222 group m16c family table 1.2. product list type no. rom capacity ram capacity package type remarks M30222fgfp 100p6s-a M30222fggp 100p6q-a 260 kbytes 20 kbytes flash table 1.2 shows the product list for the M30222 family.
1-8 under development specifications in this manual are tentative and subject to change rev. g description mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer pin description table 1.3. pin description for M30222 group pin name signal name i/o type function vcc, vss power supply input supply 2.7 to 5.5v to the vcc pin and 0v to vss vdc voltage down converter input connects capacitor from vdc to vss; or if not using vdc, connect 3.3v to vdc pin. cnvss cnvss this pin is used to enable flash programming. connect the pull-down resistor from cnvss to vss. connect cnvss to enable flash programming. reset reset input input an l on this input resets the microcomputer. xin, xout main clock input/output these pins are provided for the main clock generating circuit. connect a ceramic reso- nator or crystal between the xin and the xout pins. to use an externally derived clock, input it to the xin. p8 4 /p8 5 i/o port input/output these pins are provided for the subclock generating circuit. connect a ceramic reso- nator or crystal between the xcin pin and leave the xcout pin open. these pins also function as cmos i/o ports. xcout/xcin subclock input/output avcc analog power supply + reference input this pin is a power supply input for the a-d converter. connect this pin to vcc. avss analog power supply + reference input this pin is a power supply input for a-d converter. connect this pin to vss. vref reference voltage input input this pin is a reference voltage input for the a-d converter. p3 0 to p3 7 i/o port p3 input/output this is an 8-bit cmos i/o port. it has an input/output direction register that allows the user to set each pin for input or output individually. when used for input, the port can be set by software to have or not have a pull resistor in units of four bits. rtp0_0 to rtp3_1 output seg24 to seg31 output pins in this port also function as seg output for lcd and output for real-time port. p4 0 to p4 7 i/o port p4 input/output this is an 8-bit i/o port equivalent to p3. seg32 to seg39 output pins in port 4 also function as seg outputs for lcd. rtp4_0 to rtp7_1 output pins in port 4 also function as real-time port. p6 0 to p6 7 i/o port p6 input/output this is an 8-bit i/o port equivalent to p3. ki0 to ki7 input pins in port 6 also function as key-input interrupts. uart0, uart1 input/output pins in port 6 also function as transmit, receive, clock, and cts /rts pins for uart0, uart1. p7 0 to p7 7 i/o port p7 input/output this is an 8-bit i/o port equivalent to p3. uart2 input/output some pins in port 7 serve as transmit, receive, clock, and cts /rts for uart2. uart2 provides i 2 c serial communications. timer a/b input/output some pins in port 7 serve as input/output for timer a and timer b. int4 input pins p7 6 and p7 7 function as inputs for int4 . three-phase output some pins in port 7 function as three-phase outputs for v, v , w, and w . p8 0 to p8 2 , p8 6 i/o port p8 input/output p8 0 to p8 2 , p8 6 are i/o ports equivalent to p3. timer a input/output some pins in port 8 serve as input/output for timer a and timer b. int5 input pins p8 0 and p8 1 function as inputs for int5. three-phase output pins p8 0 and p8 1 function as inputs three-phase outputs for u and u . p8 3 nmi input p8 3 is an input only port that also functions for nmi . the nmi interrupt is generated when the input at this pin changes from h to l. the nmi function cannot be can- celled using software. the pull-up resistor cannot be set for this pin.
1-9 under development mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer specifications in this manual are tentative and subject to change rev. g description pin name signal name i/o type function p9 0 to p9 7 i/o port p9 input/output this is an 8-bit i/o equivalent to p3. sio 3/4 input/output pins in port 9 function as transmit, receive and clock for sio3 and sio4. timer b input some pins in port 9 serve as tb3 and tb4 pins. d-a output p9 3 and p9 4 can be configured to function as a digital to analog output. int2 , int3 input pin p9 0 and p9 7 can be configured as int2 and int3 . anex0 output these pins are used to connect to an optional external op amp. anex1 input p10 0 to p10 7 i/o port 10 input/output this is an 8-bit i/o port equivalent to p3. an0 to an7 input pins in port 10 function as analog inputs. int6 , int7 input p10 6 and p10 7 function as inputs for int6 and int7 . seg0 to seg23 seg drive pins pins in this port function as seg output for lcd drive circuit. com0 to com3 com ports pins in this port function as com output for lcd drive circuit. vl1 to vl3 power supply for lcd driver power supply input for lcd drive circuit.
1-10 under development specifications in this manual are tentative and subject to change rev. g memory mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer operation of functional blocks the M30222 group accommodates certain units in a single chip. these units include rom and ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as timers, serial i/o, d-a converter, dmac, crc calculation circuit, a-d converter, lcd, and i/o ports. the following explains each unit. memory figure 1.5 is a memory map of the M30222 group. the linear address space of 1m bytes extends from address 00000 16 to fffff 16 . from fffff 16 down is rom. for example, in the M30222fg-xxxfp, there is 256k bytes of internal rom from c0000 16 to fffff 16 . the vector table for fixed interrupts such as the reset and nmi are mapped to fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. from 00400 16 up is ram. for example, in the M30222fg-xxxfp, 20k bytes of internal ram is mapped to the space from 00400 16 to 053ff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr area is mapped to 00000 16 to 003ff 16 . this area accommodates the control registers for periph- eral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. tables 1.5 to 1.9 show the location of peripheral unit control registers. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. fig. 1.5. memory map 00000 16 yyyyy 16 fffff 16 00400 16 xxxxx 16 d0000 16 internal rom area sfr area for details, see tables 1.5-1.9 internal ram area internal reserved area c0000 16 053ff 16 M30222mg/fg/gp address xxxxx 16 type no. address yyyyy 16 ffe00 16 fffdc 16 fffff 16 undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc nmi
1-11 under development specifications in this manual are tentative and subject to change rev. g cpu mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer central processing unit (cpu) the cpu has a total of 13 registers shown in figure 1.6. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h/r1h), and low-order bits as (r0l/r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0/r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). (3) frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. fig. 1.6. central processing unit register h l b15 b8 b7 b0 r0 (note) h l b15 b8 b7 b0 r1 (note) r2 (note) b15 b0 r3 (note) b15 b0 a0 (note) b15 b0 a1 (note) b15 b0 fb (note) b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 hl program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these registers consist of two register banks. c d z s b o i u ipl
1-12 under development specifications in this manual are tentative and subject to change rev. g cpu mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (4) program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. (5) interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 1.7 shows the flag register (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is ?1?, a single-step interrupt is generated after instruction execution. this flag is cleared to ?0? when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to ?1? when an arithmetic operation resulted in 0; otherwise, cleared to ?0?. ? bit 3: sign flag (s flag) this flag is set to ?1? when an arithmetic operation resulted in a negative value; otherwise, cleared to ?0?. ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is ?0? ; register bank 1 is selected when this flag is ?1?. ? bit 5: overflow flag (o flag) this flag is set to ?1? when an arithmetic operation resulted in overflow; otherwise, cleared to ?0?. ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is ?0?, and is enabled when this flag is ?1?. this flag is cleared to ?0? when the interrupt is acknowledged. ? bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is ?0? ; user stack pointer (usp) is selected when this flag is ?1?. this flag is cleared to ?0? when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed.
1-13 under development specifications in this manual are tentative and subject to change rev. g cpu mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.7. flag register ? bits 8 to 11: reserved area ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ? bit 15: reserved area. carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priorit flag register (flg) c d z s b o i u ipl b0 b15 reserved area
under development specifications in this manual are tentative and subject to change rev. g reset mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer 1-14 reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see ?software reset? for details.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level ?l? (0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to the ?h? level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure 1.8 shows an example reset circuit. figure 1.9 shows a reset sequence. table 1.4 shows the pin status when reset pin level is "l". reset v cc 0.8v reset v cc 0v 0v 5v 5v 4.0v example when vcc = 5v status pin name p3, p4 p6 to p10 input port (with a pull-up resistor) input port (floating) seg0 to seg23 "h" level is output com0 to com3 "h" level is output fig. 1.8. example of reset circuit fig. 1.9. reset sequence table 1.4. pin status when reset pin level is "l" bclk bclk 24cycles x in reset address content of reset vector ffffe 16 ffffc 16 more than 20 cycles are needed
1-15 under development specifications in this manual are tentative and subject to change rev. g special function registers mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer value after reset sfr address register name acronym b7 b6 b5b4 b3 b2 b1 b0 page number 0000 16 0001 16 0002 16 0003 16 0004 16 processor mode register 0 pm0 00 16 1.19 0005 16 processor mode register 1 pm1 000 1.19 0006 16 system clock control register 0 cm0 48 16 1.23 0007 16 system clock control register 1 cm1 20 16 1.23 0008 16 0009 16 address match interrupt enable register aier 00 1.53 000a 16 protect register prcr 0000 1.34 000b 16 000c 16 000d 16 000e 16 watchdog timer start register wdts 1.57 000f 16 watchdog timer control register wdc 000 1.57 0010 16 1.53 0011 16 1.53 0012 16 address match interrupt register 0 rmad0 00 16 1.53 0013 16 0014 16 1.53 0015 16 1.53 0016 16 address match interrupt register 1 rmad1 00 16 1.53 0017 16 0018 16 vdc control register vdcc 00 00 1.29 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 1.62 0021 16 1.62 0022 16 dma0 source pointer sar0 ? 1.62 0023 16 0024 16 1.62 0025 16 1.62 0026 16 dma0 destination pointer dar0 ? 1.62 0027 16 0028 16 1.62 0029 16 dma0 transfer counter trc0 ? 1.62 002a 16 002b 16 002c 16 dma0 control register dm0con 000000 1.61 002d 16 002e 16 002f 16 0030 16 1.62 0031 16 1.62 0032 16 dma1 source pointer sar1 ? 1.62 0033 16 0034 16 1.62 0035 16 1.62 0036 16 dma1 destination pointer dar1 ? 1.62 0037 16 0038 16 1.62 0039 16 dma1 transfer counter tcr1 ? 1.62 003a 16 003b 16 003c 16 dma1 control register dm1con 000000 1.61 003d 16 003e 16 003f 16 special function registers ? = undefined table 1.5. location and value after reset of peripheral unit control registers (1)
1-16 under development specifications in this manual are tentative and subject to change rev. g special function registers mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer value after reset sfr address register name acronym b7 b6 b5b4 b3 b2 b1 b0 page number 0044 16 int3 interrupt control register si/o4 interrupt control register int3ic s4ic 00000 0 1.39 0045 16 timer b5 interrupt control register tb5ic 0000 1.39 0046 16 timer b4 interrupt control register tb 4ic 0000 1.39 0047 16 timer b3 interrupt control register tb3ic 0000 1.39 0048 16 int7 interrupt control register int7ic 00000 0 1.39 0049 16 int6 interrupt control register int6ic 00000 0 1.39 004a 16 bus collision detection interrupt control register bcnic 0000 1.39 004b 16 dma0 interrupt control register dm0ic 0000 1.39 004c 16 dma1 interrupt control register dm1ic 0000 1.39 004d 16 key input interrupt control register kupic 0000 1.39 004e 16 a-d conversion interrupt control register adic 0000 1.39 004f 16 uart2 transmit interrupt control register s2tic 0000 1.39 0050 16 uart2 receive interrupt control register s2ric 0000 1.39 0051 16 uart0 transmit interrupt control register s0tic 0000 1.39 0052 16 uart0 receive interrupt control register s0ric 0000 1.39 0053 16 uart1 transmit interrupt control register s1tic 0000 1.39 0054 16 uart1 receive interrupt control register s1ric 0000 1.39 0055 16 timer a0 interrupt control register ta0ic 0000 1.39 0056 16 timer a1 interrupt control register ta1ic 0000 1.39 0057 16 timer a2 interrupt control register ta2ic 0000 1.39 0058 16 timer a3 interrupt control register int4 interrupt control register ta3ic int4ic 00000 0 1.39 0059 16 timer a4 interrupt control register int5 interrupt control register ta4ic int5ic 00000 0 1.39 005a 16 timer b0 interrupt control register tb0ic 0000 1.39 005b 16 timer b1 interrupt control register tb1ic 0000 1.39 005c 16 timer b2 interrupt control register tb2ic 0000 1.39 005d 16 int0 interrupt control register int0ic 00000 0 1.39 005e 16 int1 interrupt control register int1ic 00000 0 1.39 005f 16 int2 interrupt control register si/o3 interrupt control register int2ic s3ic 00000 0 1.39 0100 16 lcd ram0 lram0 ??????? ? 1.146 0101 16 lcd ram1 lram1 ??????? ? 1.146 0102 16 lcd ram2 lram2 ??????? ? 1.146 0103 16 lcd ram3 lram3 ??????? ? 1.146 0104 16 lcd ram4 lram4 ??????? ? 1.146 0105 16 lcd ram5 lram5 ??????? ? 1.146 0106 16 lcd ram6 lram6 ??????? ? 1.146 0107 16 lcd ram7 lram7 ??????? ? 1.146 0108 16 lcd ram8 lram8 ??????? ? 1.146 0109 16 lcd ram9 lram9 ??????? ? 1.146 010a 16 lcd ram10 lram10 ??????? ? 1.146 010b 16 lcd ram11 lram11 ??????? ? 1.146 010c 16 lcd ram12 lram12 ??????? ? 1.146 010d 16 lcd ram13 lram13 ??????? ? 1.146 010e 16 lcd ram14 lram14 ??????? ? 1.146 010f 16 lcd ram15 lram15 ??????? ? 1.146 0110 16 lcd ram16 lram16 ??????? ? 1.146 0111 16 lcd ram17 lram17 ??????? ? 1.146 0112 16 lcd ram18 lram18 ??????? ? 1.146 0113 16 lcd ram19 lram19 ??????? ? 1.146 0120 16 lcd mode register lcdm 0 000000 1.143 0121 16 0122 16 segment output enable register seg 00 16 1.143 0123 16 0124 16 lcd frame frequency counter lcdtim 1.143 0125 16 0126 16 key input mode register kupm 00 1.52 0127 16 0128 16 0129 16 0130 16 lcd expansion register lexp 00 16 1.144 0131 16 0132 16 lcd clock divide counter lcdc 1.144 0133 16 ? = undefined table 1.6. location and value after reset of peripheral unit control registers (2)
1-17 under development specifications in this manual are tentative and subject to change rev. g special function registers mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.7. location and value after reset of peripheral unit control registers (3) ? = undefined value after reset sfr address register name acronym b7 b6 b5b4 b3 b2 b1 b0 page number 0340 16 timer b3, 4, 5 count start flag tbsr 000 1.85 0341 16 0342 16 0343 16 timer a1-1 register ta11 1.94 0344 16 0345 16 timer a2-1 register ta21 1.94 0346 16 0347 16 timer a4-1 register ta41 1.94 0348 16 three-phase pwm control register 0 invc0 00 16 1.92 0349 16 three-phase pwm control register 1 invc1 00 16 1.92 034a 16 three-phase output buffer register 0 idb0 3f 16 1.93 034b 16 three-phase output buffer register 1 idb1 3f 16 1.93 034c 16 dead time timer dtt 1.93 034d 16 timer b2 interrupt occurrence frequency set counter ictb2 1.93 034e 16 034f 16 0350 16 0351 16 timer b3 register tb3 1.85 0352 16 0353 16 timer b4 register tb4 1.85 0354 16 0355 16 timer b5 register tb5 1.85 035b 16 timer b3 mode register tb3mr 00 0000 1.87 1.88, 1.90 035c 16 timer b4 mode register tb4mr 00 0000 1.87 1.88, 1.90 035d 16 timer b5 mode register tb5mr 00 0000 1.87 1.88, 1.90 035e 16 interrupt cause select register 0 ifsr0 00 16 1.49 035f 16 interrupt cause select register 1 ifsr1 00 16 1.49 0360 16 si/o3 transmit/receive register s3trr 1.138 0361 16 0362 16 si/o3 control register s3c 40 16 1.138 0363 16 si/o3 bit rate generator s3brg 1.138 0364 16 si/o4 transmit/receive register s4trr 1.138 0365 16 0366 16 si/o4 control register s4c 40 16 1.138 0367 16 si/o4 bit rate generator s4brg 1.138 036c 16 clock divided control register cdcc 0 1.24 036d 16 036e 16 clock divided counter cdc 1.24 0375 16 uart2 special mode register 3 u2smr3 00 16 1.112 1.130 0376 16 uart2 special mode register 2 u2smr2 00 16 1.112, 1.134 0377 16 uart2 special mode register u2smr 00 16 1.111, 1.130 0378 16 uart2 transmit/receive mode register u2mr 00 16 1.108, 1.114, 1.120 0379 16 uart2 bit rate generator u2brg 1.107 037a 16 037b 16 uart2 transmit buffer register u2tb 1.107 037c 16 uart2 transmit/receive control register 0 u2c0 08 16 037d 16 uart2 transmit/receive control register 1 u2c1 02 16 1.110 037e 16 037f 16 uart2 receive buffer register u2rb 1.102
1-18 under development specifications in this manual are tentative and subject to change rev. g special function registers mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer note: this register only exists in flash memory version value after reset sfr address register name acronym b7 b6 b5b4 b3 b2 b1 b0 page number 0380 16 count start flag tabsr 00 16 1.71, 1.85, 1.94 0381 16 clock prescaler reset flag cpsrf 0 1.72, 1.85 0382 16 one-shot start flag onsf 00 00000 1.72 0383 16 trigger select register trgsr 00 16 1.72, 1.94 0384 16 up-down flag udf 00 16 1.71 0385 16 0386 16 0387 16 timer a0 ta0 1.71 0388 16 0389 16 timer a1 ta1 1.71, 1.90 038a 16 038b 16 timer a2 ta2 1.71, 1.90 038c 16 038d 16 timer a3 ta3 1.71 038e 16 038f 16 timer a4 ta4 1.71, 1.90 0390 16 0391 16 timer b0 tb0 1.83 0392 16 0393 16 timer b1 tb1 1.83 0394 16 0395 16 timer b2 tb2 1.83, 1.90 0396 16 timer a0 mode register ta0mr 00 16 1.70, 1.73, 1.74, 1.77, 1.78 0397 16 timer a1 mode register ta1mr 00 16 1.70, 1.73, 1.74, 1.77, 1.78, 1.95 0398 16 timer a2 mode register ta2mr 00 16 1.70, 1.73, 1.74, 1.77, 1.78, 1.95 0399 16 timer a3 mode register ta3mr 00 16 1.70, 1.72, 1.73, 1.77, 1.78 039a 16 timer a4 mode register ta4mr 00 16 1.70, 1.73, 1.74, 1.77, 1.78, 1.95 039b 16 timer b0 mode register tb0mr 00 0000 1.84, 1.87, 1.90 039c 16 timer b1 mode register tb1mr 00 0000 1.84, 1.87, 1.90 039d 16 timer b2 mode register tb2mr 00 0000 1.84, 1.87, 1.90, 1.95 039e 16 039f 16 03a0 16 uart0 transmit/receive mode register u0mr 00 16 1.108, 1.114, 1.120 03a1 16 uart0 bit rate generator u0brg 1.107 03a2 16 03a3 16 uart0 transmit buffer register u0tb 1.107 03a4 16 uart0 transmit/receive control register 0 u0c0 08 16 1.109 03a5 16 uart0 transmit/receive control register 1 u0c1 02 16 1.110 03a6 16 03a7 16 uart0 receive buffer register u0rb 1.107 03a8 16 uart1 transmit/receive mode register u1mr 00 16 1.108, 1.114, 1.120 03a9 16 uart1 bit rate generator u1brg 1.107 03aa 16 03ab 16 uart1 transmit buffer register u1tb 1.107 03ac 16 uart1 transmit/receive control register 0 u1c0 08 16 1.109 03ad 16 uart1 transmit/receive control register 1 u1c1 02 16 1.110 03ae 16 03af 16 uart1 receive buffer register u1rb 1.107 03b0 16 uart transmit/receive control register 2 ucon 0000000 1.111 03b1 16 03b2 16 03b3 16 03b4 16 flash memory control register (note) fmcr 0001 1.176 03b5 16 03b6 16 03b7 16 03b8 16 dma0 request cause select register dm0sl 00 16 1.60 03b9 16 03ba 16 dma1 dm1sl 00 16 1.61 03bb 16 03bc 16 03bd 16 crc data register crcd 1.164 03be 16 crc input register crcin 1.164 ? = undefined
1-19 under development specifications in this manual are tentative and subject to change rev. g special function registers mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.9. location and value after reset of peripheral unit control registers (5) value after reset sfr address register name acronym b7 b6 b5b4 b3 b2 b1 b0 page number 03c0 16 03c1 16 a-d register 0 ad0 1.154 03c2 16 03c3 16 a-d register 1 ad1 1.154 03c4 16 03c5 16 a-d register 2 ad2 1.154 03c6 16 03c7 16 a-d register 3 ad3 1.154 03c8 16 03c9 16 a-d register 4 ad4 1.154 03ca 16 03cb 16 a-d register 5 ad5 1.154 03cc 16 03cd 16 a-d register 6 ad6 1.154 03ce 16 03cf 16 a-d register 7 ad7 1.154 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 a-d control register 2 adcon2 0000 0 1.154 03d5 16 03d6 16 a-d control register 0 adcon0 00000 1.153, 1.155, 1.156, 1.157, 1.158, 1.159 03d7 16 a-d control register 1 adcon1 00 16 1.153, 1.155, 1.156, 1.157, 1.158, 1.159 03d8 16 d-a register 0 da0 1.163 03d9 16 03da 16 d-a register 1 da1 1.163 03db 16 03dc 16 d-a control register dacon 00 16 1.163 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 port p3 p3 1.170 03e6 16 03e7 16 port p3 direction register pd3 00 16 1.170 03e8 16 port p4 p4 1.170 03e9 16 03ea 16 port p4 direction register pd4 00 16 1.170 03eb 16 03ec 16 port p6 p6 1.170 03ed 16 port p7 p7 1.170 03ee 16 port p6 direction register pd6 00 16 1.170 03ef 16 port p7 direction register pd7 00 16 1.170 03f0 16 port p8 p8 000000 0 1.170 03f1 16 port p9 p9 1.170 03f2 16 port p8 direction register pd8 0 0000 0 1.170 03f3 16 port p9 direction register pd9 00 16 1.170 03f4 16 port p10 p10 1.170 03f5 16 03f6 16 port p10 direction register pd10 00 16 1.170 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 pull-up control register 0 pur0 00 16 1.171 03fd 16 pull-up control register 1 pur1 00 16 1.171 03fe 16 pull-up control register 2 pur2 00 16 1.171 03ff 16 real-time port control register rtp 000 0 1.83 ? = undefined table 1.8. location and value after reset of peripheral unit control registers (4)
1-20 under development specifications in this manual are tentative and subject to change rev. g software reset mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer software reset writing ?1? to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has the same effect as a hardware reset. the contents of internal ram are preserved. figure 1.10 shows processor mode register 0 and 1. fig. 1.10. processor mode register 0 and 1 note : set bit 1 of the protect register (address 000a 16 ) to ? 1 ? when writing new values processor mode register 1 (note ) symbol address when reset pm1 0005 16 0xxxxx00 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. reserved bit must always be set to ? 0 ? 0 processor mode register 0 (note) symbol address when reset pm0 0004 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pm03 software reset bit the device is reset when this bit is set to ? 1 ? . the value of this bit is ? 0 ? when read. note : set bit 1 of the protect register (address 000a 16 ) to ? 1 ? when writing new values to this register. 0 0 0 nothing is assigned. nothing is assigned. reserved bit must always be set to "0" o o write "0" when writing to this these bits. if read, the value is indeterminate. pm17 wait bit 0 : no wait state 1 : wait state inserted 0 0 to this register. write "0" when writing to this these bits. if read, the value is indeterminate. write "0" when writing to this these bits. if read, the value is indeterminate.
1-21 under development specifications in this manual are tentative and subject to change rev. g clock generating circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer clock generating circuit the clock generating circuit contains two oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units. table 1.10 shows some examples of the main clock and subclock generating circuits. table 1.10. main clock and sub-clock generating circuits figure 1.11 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure 1.12 shows some ex- amples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures 1.11 and 1.12 vary with each oscil- lator used. use the values recommended by the manufacturer of your oscillator. note: max. voltage is the same as vdc main clock generating circuit sub-clock generating circuit use of clock operating clock source for cpu operating clock source for internal peripheral operating clock source count clock source for timers a/b operating clock source for lcd usable oscillator ceramic or crystal oscillator crystal oscillator pins to connect oscillator xin, xout xcin, xcout oscillation stop/restart function available available oscillator status immediately after reset oscillating stopped other externally derived clock can be input (note) fig. 1.11. examples of main clock microcomputer x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction.
1-22 under development specifications in this manual are tentative and subject to change rev. g clock generating circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.13. clock generating circuit fig. 1.12. examples of sub-clock figure 1.13 shows a block diagram of the clock generating circuit. microcomputer x cin x cout externally derived clock open vdc (note 2) vss note 1: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x cin and x cout following the instruction. microcomputer (built-in feedback resistor) x cin x cout r c cin c cout (note 1) note 2: reference xcin to vdc supply. sub clock cm04 f c32 cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 x cin cm10 "1" write signal 1/32 x cout q s r wait instruction x out main clock cm05 f c cm02 f 1 q s r nmi interrupt request level judgment output reset software reset f c cm07=0 cm07=1 f ad divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a details of divider x in f 8 f 32 c b b 1/2 c bclk f c132 f c1 cm14=0 cm14=1
1-23 under development specifications in this manual are tentative and subject to change rev. g clock generating circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to the bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock, after switching the operating clock source of cpu to the sub-clock, reduces the power dissipation. after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. this bit changes to ?1? when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (2) sub-clock the sub-clock is generated by the sub-clock oscillation circuit. no sub-clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub-clock can be selected as the bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub-clock oscillation has fully stabilized before switching. after the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. this bit changes to ?1? when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. the bclk is derived by dividing the main clock by 8 after a reset. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to ?1? when shifting from high-speed/ medium-speed to stop mode and at reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) peripheral function clock (f 1 , f 8 , f 32 , f ad ) the clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. the periph- eral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to ?1? and then executing a wait instruction. (5) f c132 this clock is derived by dividing the sub-clock by 1 or 32. the clock is selected by f c132 clock select bit (bit4 at address 0007 16 ). it is used for the timer a and timer b counts, intermittent pull up operation of key input. (6) f c this clock has the same frequency as the sub-clock. it is used for the bclk and for the watchdog timer. figure 1.14 shows the system clock control registers 0 and 1.
1-24 under development specifications in this manual are tentative and subject to change rev. g clock generating circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.14. clock control registers 0 and 1 system clock control register 0 (note 1) symbol address when reset cm0 0006 16 48 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p7 5 0 1 : f c1 output 1 0 : f 1 output 1 1 : clock divide counter output b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bits wait peripheral function clock stop bit 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 7) xcin-xout drive capacity select bit (note 2) 0 : low 1 : high 0 : i/o port 1 : xcin - xcout generation main clock (x in -x out ) stop bit (note 3, 4) 0 : main clock on 1 : main clock off main clock division select bit 0 (note 6) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note 5) 0 : xin, xout xcin, xcout 1 : note 1: set bit 0 of the protect register (address 000a 16 ) to "1" before writing to this register. note 2: changes to "1" when shifting to stop mode and at a reset. note 3: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 4: if this bit is set to "1", x out turns "h". the built-in feedback resistor remains being connected, so x in turns pulled up to x out ("h") via the feedback resistor. note 5: set subclock (x cin - x cout ) enable bit (cm04) to "1" and allow the subclock to stabilize before setting cm07 from from "0" to "1". do not write to both bits at the same time. likewise, set the main clock stop bit (cm05) to "0" and allow the subclock to stabilize before settng cm07 bit from "1" to "0". note 6: this bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 7: f c , f c132 , f c1 , f c32 is not included. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note 4) 0 : clock on 1 : all clocks off (stop mode) note 1: set bit 0 of the protect register (address 000a 16 ) to "1" before writing to this register. note 2: this bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is "0". if "1", division mode is fixed at 8. note 4: if this bit is set to "1", x out goes "h", and the built-in feedback resistor is cut off. xcin and xcout goes into high cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r w r cm16 cm17 main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 reserved bit always set to "0" 0 0 cm14 f c132 clock select bit 0 : f c32 1 : f c1 port xc select bit impedance state.
1-25 under development specifications in this manual are tentative and subject to change rev. g clock output mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.15. block diagram of clock output fig. 1.16. clock divided counter related register clock output the M30222 provides for a clock output signal (p7 3 /clk out pin) of user defined frequency. the clock output function select bit (cm00, cm01) allows you to choose the clock source from f 1 , f c1 , or a divide-by- n clock for output to the p7 3 /clk out pin. the clock divide counter is an 8-bit counter whose count source is f 32 , and its divide ratio can be set in the range of 00 16 to ff 16 . also, the clock divided counter can be controlled for start or stop by the clock divide counter start flag. figure 1.15 shows a block diagram of clock output. figure 1.16 shows a clock divided counter related register. clock source selection reload register (8) low-order 8 bits data bus low-order bits p7 5 f 1 f c1 1/2 division n+1 n=00 16 to ff 16 clock divided counter (8) example: when f(x in )=10mhz, count source = f 32 n=07 16 : approx. 19.5khz n=26 : approx. 4.0khz n=4d : approx. 2.0khz n=9b : approx. 1.0khz p7 5 /clk out f 32 address 036e 16 16 16 16 clock divided counter symbol address when reset cdc 036e 16 xx 16 function values that can be set w r b7 b0 8-bit timer 00 16 to ff 16 clock divided counter control register symbol address when reset cdcc 036c 16 0xxxxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 cdcs bit name clock divided counter start flg 0 : stop 1 : start nothing is assigned. write "0" when writing to these bits. when read, the value is indeterminate.
1-26 under development specifications in this manual are tentative and subject to change rev. g wait mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer wait mode when a wait instruction is executed, the bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but the bclk and watchdog timer stop. writing ?1? to the wait periph- eral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table 1.11 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or an interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as bclk, the clock that had been selected when the wait instruction was executed. usage precautions when switching to either wait mode or stop mode, instructions occupying four bytes either from the wait instruction or from the instruction that sets the every-clock stop bit to ?1? within the instruction queue are prefetched and then the program stops. so put at least four nops in succession either to the wait instruc- tion or to the instruction that sets the every-clock stop bit to ?1?. port clkout/ p7 5 pin when f c 1 selected when f1, clock divided counter output selected single-chip mode retains status before wait mode does not stop mode retains status before stop mode. does not stop when the wait peripheral function clock stop bit is "0". when the wait peripheral function clock stop bit is "1", the status im- mediately prior to entering wait mode is maintained. table 1.11. port status during wait mode
1-27 under development specifications in this manual are tentative and subject to change rev. g stop mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer stop mode writing "1" to all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc remains above 2v. because the oscillation , bclk, f 1 to f 32 , f c , f c132 , f c1 , f c32 and f ad stops in stop mode, peripheral functions such as the a-d converter and watchdog timer do not function. however, timer a and timer b operate provided that the event counter mode is set to an external pulse, and uart0 to uart2 functions provided an external clock is selected. table 1.12 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or an interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. if coming out of stop mode is caused by an interrupt, that interrupt routine is executed. when shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock divi- sion select bit 0 (bit 6 at address 0006 16 ) is set to ?1?. when shifting from low-speed/low power dissipa- tion mode to stop mode, the value before stop mode is retained. usage precautions (1) when returning from stop mode by hardware reset, reset pin must be set to ?l? level until main clock oscillation is stabilized. (2) when switching to either wait mode or stop mode, instructions occupying four bytes either from the wait instruction or from the instruction that sets the every-clock stop bit to ?1? within the instruction queue are prefetched and then the program stops. put at least four nops in succession either to the wait instruction or to the instruction that sets the every-clock stop bit to ?1?. table 1.12 port status during stop mode pin status port clkout/ p7 5 when fc1 selected when f1, clock divided output selected retains status before stop mode "h" retains status before stop mode mode
1-28 under development specifications in this manual are tentative and subject to change rev. g status transition of bclk mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table 1.13 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. when reset, the device starts in division by 8 mode. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to ?1? when shifting from high-speed/medium-speed to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. the following shows the operational modes of bclk. (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. when reset, the device starts operating from this mode. before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. when going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is divided by 1 to obtain the bclk. (6) low-speed mode f c is used as the bclk. note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub- clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) low power dissipation mode f c is the bclk and the main clock is stopped. note : before the count source for bclk can be changed from x in to x cin or vice versa, the clock to which the count source is going to be switched must be oscillating stably. allow time in software for the source to stabilize before switching over the clock.
1-29 under development specifications in this manual are tentative and subject to change rev. g status transition of bclk mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.13. operating modes dictated by settings of system clock control registers 0 and 1 cm17 cm16 cm07 cm06 cm05cm04 bclk operating mode 01000i nvalid divide by 2 10000i nvalid divide by 4 invalid invalid 0 1 0 invalid divide by 8 11000i nvalid divide by 16 01000i nvalid none invalid invalid 1 invalid 0 1 low-speed invalid invalid 1 invalid 1 1 low power dissipation
1-30 under development specifications in this manual are tentative and subject to change rev. g voltage down converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer voltage down converter the voltage down converter (vdc) is a bandgap reference based voltage regulator used for generating a low-voltage supply. the vdc block inputs the external supply v cc (up to 5.5 volts) and generates a 3.3- volt (nominal) supply (vdd). table 1.14 describes the specified voltage regulation. the vdc is pro- grammable in terms of drive limit and power level. in low power mode, the vdc can source up to 20ma and uses less than 10ua bias current. in high-power mode, the vdc can source up to 200ma. there is a programmable option to limit the current of the vdc in high-power mode to about 80ma. the vdc default state (from reset) is high-power mode with current limiting enabled. the current limiting is en- abled at reset in order to avoid a large in-rush current to an external hold capacitor (required) on the vdc pin. once the external hold capacitor is charged, the current limiter can be disabled in software. figures 1.17 and 1.18 describe the programmable features of the vdc. the external hold capacitor is required to stabilize the vdc and to minimize voltage ripple on the 3.3 volt supply during operation. table 1.15 describes the external hold capacitor requirements. table 1.15. required external components figure 1.17. vdc control/status register component value material external hold capacitor 0.1 f +/- 20% ceramic table 1.14. vdc voltage regulations signal description package supply (vcc) range: 2.7v to 5.5v (input to vdc) internal supply (vdd) 3.3v (nominal) +/- 10% (output from vdc) or vcc - 200mv @ icc (avg) <15 ma (note) note: whichever is smaller voltage down converter control register symbol address when reset vdcc 0018 16 xxx00x00 2 b7 b6 b5 b4 b3 b2 b1 b0 hpower vdcc0 0 0 : vdc enabled 0 1 : reserved 1 0 : reserved 1 1 : vdc disabled b1 b0 vdcc1 ilimen nothing is assigned. write "0" when writing to these bits. if read, the function bit symbol w r _ _ _ 0 : current limit enabled 1 : current limit disabled 0 : high power 1 : low power value is indeterminate. nothing is assigned. write "0" when writing to this bit. if read, the value is indeterminate. _
1-31 under development specifications in this manual are tentative and subject to change rev. g voltage down converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.18. vdc functional block diagram (0) (1) en vcc current limit high power regulator bandgap reference external supply (5 v) vcc (0) (1) en vcc low power regula tor vdcc0 vdcc1 hpower ilimen external hold capacit or 0.1 f 3.3 v supply vdc control status register vdc pin (1.22v)
1-32 under development specifications in this manual are tentative and subject to change rev. g power control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer power control the following is a description of the three available power control modes: modes power control is available in three modes. (a) normal operation mode ? high-speed mode divide-by-1 frequency of the main clock becomes the bclk. the cpu operates with the internal clock selected. each peripheral function operates according to its assigned clock. ? medium-speed mode divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the bclk. the cpu operates according to the internal clock selected. each peripheral function operates according to its as- signed clock. ? low-speed mode f c becomes the bclk. the cpu operates according to the fc clock. the fc clock is supplied by the secondary clock. each peripheral function operates according to its assigned clock. ? low power consumption mode the main clock operating in low-speed mode is stopped. the cpu operates according to the f c clock. the fc clock is supplied by the secondary clock. the only peripheral functions that operate are those with the sub- clock selected as the count source. (b) wait mode the cpu operation is stopped. the oscillators do not stop. (c) stop mode all oscillators stop. the cpu and all built-in peripheral functions stop. this mode, among the three modes listed here, is the most effective in decreasing power consumption. figure 1.19 is the state transition diagram of the above modes.
1-33 under development specifications in this manual are tentative and subject to change rev. g power control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.19. state transition diagram of power control mode all oscillators stopped stop mode medium-speed mode (divided-by-8 mode) reset normal mode wait instruction interrupt wait instruction interrupt cm10 = "1" cm10 = "1" interrupt interrupt state transitions for stop and wait modes main clock is oscillating sub clock is stopped medium-speed mode (divided-by-8 mode) bclk : f(x in )/8 cm07 = "0" cm06 = "1" high-speed mode bclk ; f(x in ) cm07 = "0" cm06 = "0" cm17 = "0" cm16 = "0" medium-speed mode (divided-by-4 mode) bclk : f(x in )/4 cm07 = "0" cm06 = "0" cm17 = "1" cm16 = "0" bclk ; f(x in )/2 cm07 = "0" cm06 = "0" cm17 = "0" cm16 = "1" medium-speed mode (divided-by-2 mode) medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = "0" cm06 = "0" cm17 = "1" cm16 = "1" medium-speed mode (divided-by-8 mode) bclk : f(x in )/8 cm07 = "0" cm06 = "1" high-speed mode bclk ; f(x in ) cm07 = "0" cm06 = "0" cm17 = "0" cm16 = "0" medium-speed mode (divided-by-4 mode) bclk : f(x in )/4 cm07 = "0" cm06 = "0" cm17 = "1" cm16 = "0" bclk ; f(x in )/2 cm07 = "0" cm06 = "0" cm17 = "0" cm16 = "1" medium-speed mode (divided-by-2 mode) medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = "0" cm06 = "0" cm17 = "1" cm16 = "1" cm04 = "0" main clock is oscillating sub clock is stopped cm04 = "1" main clock is oscillating sub clock is oscillating cm06 = "0" (notes 1, 3) cm07 = "0" (note 1) cm06 = "0" (note 3) cm04 = "1" cm07 = "1" (note 2) cm05 = "1" cm05 = "0" cm04 = "1" (notes 1, 3) cm04 = "0" cm06 = "1" cm07 = "0" (note 1, 3) cm07 = "1" (note 2) cm07 = "0" (note 1) cm06 = "1" cm04 = "0" all oscillators stopped stop mode all oscillators stopped stop mode high speed / medium-speed mode low-speed / low power dissipation mode cpu operation stopped wait mode cpu operation stopped wait mode cpu operation stopped wait mode cm10 = "1" wait instruction interrupt main clock is oscillating sub clock is oscillating low-speed mode bclk : f(x cin ) cm07 = "1" bclk : f(x cin ) cm07 = "1" main clock is stopped sub clock is oscillating low-power dissipation mode cm05 = "1" note 1: switch clock after oscillation of main clock is sufficiently stable. note 2: switch clock after oscillation of sub clock is sufficiently stable. note 3: change cm06 after changing cm17 and cm16. note 4: transit in accordance with arrow. state transitions for normal mode
1-34 under development specifications in this manual are tentative and subject to change rev. g software wait mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer software wait a software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16 ) (note) and bits 4 to 7 of the chip select control register (address 0008 16 ). a software wait is inserted in the internal rom/ram area by setting the wait bit of the processor mode register 1. when set to ?0?, each bus cycle is executed in one bclk cycle. when set to ?1?, each bus cycle is executed in two or three bclk cycles. after the microcomputer has been reset, this bit defaults to ?0?. when set to ?1?, a wait is applied to all memory areas (two or three bclk cycles), regardless of the contents of bits 4 to 7 of the chip select control register. set this bit after referring to the recom- mended operating conditions (main clock input oscillation frequency) of the electric characteristics. the sfr area is always accessed in two bclk cycles regardless of the setting of these control bits. table 1.16 shows the software wait and bus cycles. note: before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000a 16 ) to ?1?. table 1.16. software wait and bus cycles area wait bit bus cycle 0 2 bclk cycles sfr internal rom/ram 1 1 bclk cycle invalid 2 bclk cycles
1-35 under development specifications in this manual are tentative and subject to change rev. g protection mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.20. protect register protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 1.20 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control register 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ), port p9 direction register (address 03f3 16 ) and vdc control register (address 0018 16 )can only be changed when the respective bit in the protect register is set to ?1?. the system clock control registers 0 and 1 write-enable bit (bit 0 at 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at 000a 16 ) do not automatically return to ?0? after a value has been written to an address. the program must therefore be written to return these bits to ?0?. protect register symbol address when reset prcr 000a 16 xxxx0000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 prc2 enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) enables writing to port p9 direction register (address 03f3 16 ) and si/oi control register (i=3,4) (addresses 0362 16 and 0366 16 ) (note ) 0 : write-inhibited 1 : write-enabled w r nothing is assigned. note: writing a value to these addresses after ? 1 ? is written to this bit returns the bit to ? 0 ? . other bits do not automatically return to ? 0 ? and they must therefore be reset by the program prc3 0 : write-inhibited 1 : write-enabled enables writing to vdc control register (address 0018 16 ) o o write "0" when writing to these bits. if read, the value is indeterminate.
1-36 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer overview of interrupts types of interrupts figure 1.21 lists the types of interrupts. ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 1.21. classification of interrupts software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. ? undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ? overflow interrupt an overflow interrupt occurs when an executing arithmetic instruction overflows. the following instruc- tions will set an o flag when an overflow occurs : abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ? brk interrupt a brk interrupt occurs when executing the brk instruction. ? int interrupt an int interrupt occurs when specifying one of the software interrupt numbers 0 through 63 and execut- ing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o inter- rupts, so executing the int instruction executes the same interrupt routine as the peripheral i/o interrupt. the stack pointer (sp), used for the int interrupt, is dependent on which software interrupt number is selected. as far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. the u flag is set to "0" selecting the interrupt stack pointer then the interrupt sequence is executed. when returning from the interrupt routine, the u flag is returned to its previous state before accepting the interrupt request. as far as software numbers 32 through 63 are concerned, the stack pointer does not change. interrupt software hardware special peripheral i/o (note) undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction reset nmi dbc watchdog timer single step address matched note: peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system.
1-37 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer hardware interrupts hardware interrupts are classified into two types ? special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ? reset reset occurs if an ?l? is input to the reset pin. ? nmi interrupt an nmi interrupt occurs if an ?l? is input to the nmi pin. ? dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ? watchdog timer interrupt generated by the watchdog timer. ? single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to ?1?, a single-step interrupt occurs after one instruction is executed. ? address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to ?1?. if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ? bus collision detection interrupt this is an interrupt that the serial i/o bus collision detection generates. ? dma0 interrupt, dma1 interrupt these are interrupts that dma generates. ? key-input interrupt a key-input interrupt occurs if an ?l? is input to the ki pin. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? sio3, sio4 interrupt these are the interrupts for sio3, sio4 ? uart0, uart1, uart2/nack transmission interrupt these are interrupts that the serial i/o transmission generates. ? uart0, uart1, uart2/ack reception interrupt these are interrupts that the serial i/o reception generates. ? timer a0 interrupt through timer a4 interrupt these are interrupts that timer a generates ? timer b0 interrupt through timer b5 interrupt these are interrupts that timer b generates. ? int0 interrupt through int7 interrupt an int interrupt occurs if either a rising edge or a falling edge or a both edge is input to one of the int pins.
1-38 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer interrupts and interrupt vector tables if an interrupt request is accepted, program execution branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 1.22 shows the format for specifying the address. two types of interrupt vector tables are available ? fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. ? fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 1.17 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. figure 1.22. format for specifying interrupt vector addresses table 1.17. interrupts assigned to the fixed vector tables and addresses of vector tables mid address low address 0 0 0 0 high address 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb interrupt source vector table addresses remarks address (l) t o address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on overflow brk instruction fffe4 16 to fffe7 16 if thisvector contains fffff 16, program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 requires address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to ffff3 16 dbc (note) ffff4 16 to ffff7 16 do not use nmi ffff8 16 to ffffb 16 external interrupt by input to nmi pin reset ffffc 16 to fffff 16 note: interrupts used for debugging purposes only.
1-39 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.18. interrupts assigned to the variable vector tables and addresses of vector tables software interrupt number interrupt source vector table address address (l) to address (h) remarks not masked by i flag +0 to +3 (note 1) brk instruction software interrupt number 0 +44 to +47 (note 1) software interrupt number 11 +48 to +51 (note 1) software interrupt number 12 +52 to +55 (note 1) software interrupt number 13 +56 to +59 (note 1) software interrupt number 14 +68 to +71 (note 1) software interrupt number 17 +72 to +75 (note 1) software interrupt number 18 +76 to +79 (note 1) software interrupt number 19 +80 to +83 (note 1) software interrupt number 20 +84 to +87 (note 1) software interrupt number 21 +88 to +91 (note 1) software interrupt number 22 +92 to +95 (note 1) software interrupt number 23 +96 to +99 (note 1) software interrupt number 24 +100 to +103 (note 1) software interrupt number 25 +104 to +107 (note 1) software interrupt number 26 +108 to +111 (note 1) software interrupt number 27 +112 to +115 (note 1) software interrupt number 28 +116 to +119 (note 1) software interrupt number 29 +120 to +123 (note 1) software interrupt number 30 +124 to +127 (note 1) software interrupt number 31 +128 to +131 (note 1) software interrupt number 32 +252 to +255 (note 1) software interrupt number 63 to note 1: address relative to address in interrupt table register (intb). note 2: when iic mode is selected, nack and ack interrupts are selected. +40 to +43 (note 1) software interrupt number 10 +60 to + 63 (note 1) software interrupt number 15 +64 to +67 (note 1) software interrupt number 16 +20 to +23 (note 1) software interrupt number 5 +24 to +27 (note 1) software interrupt number 6 +28 to +31 (note 1) software interrupt number 7 +32 to +35 (note 1) software interrupt number 8 +16 to +19 (note 1) int3 / sio4 (note 3) software interrupt number 4 +36 to +39 (note 1) int6 software interrupt number 9 timer b3 timer b4 timer b5 to dma0 dma1 key input interrupt a-d uart1 transmit uart1 receive uart0 transmit uart0 receive timer a0 timer a1 timer a2 timer a3/ int4 (note 3) timer a4 / int5 (note 3) timer b0 timer b1 timer b2 int0 int1 int2 / sio3 (note 3) software interrupt bus collision detection uart2 transmit (note 2) uart2 receive (note 2) int7 not masked by i flag ~ ~ ~ ~ note 3: selected by interrupt request cause select bit (bits 4, 5, 6, 7 at address 035f 16 ) ? variable vector tables the addresses in the variable vector table can be modified, according to the user?s settings. before enabling interrupts, the user msut load the intb register with the address of the first entry in the table. the 256-byte area subsequent to the address the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 1.18 shows the interrupts assigned to the variable vector tables and addresses of vector tables. shows the interrupts assigned to the variable vector tables and addresses of vector tables.
1-40 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a maskable interrupt using the interrupt enable flag (i flag), interrupt priority level selection bits, or processor interrupt priority level (ipl). whether an interrupt request is present or absent is indicated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the cpu flag register (flg). figure 1.23 shows the memory map of the interrupt control registers. figure 1.23. memory map of the interrupt control registers. symbol address when reset intiic(i=0 to 1) 005d 16 , 005e 16 xx000000 2 int2ic/si3ic 005f 16 xx000000 2 int31c/si4ic 0044 16 xx000000 2 int4ic/ta3ic 0058 16 xx000000 2 int5/ta4ic 0059 16 xx000000 2 intiic(i= 6 to 7) 0049 16 , 0048 16 xx000000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ilvl0 ir pol interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested always set to ? 0 ? ilvl1 ilvl2 note 1 to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. for details, see the precautions for interrupts. note 2: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). (note 2) interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 bit name function bit symbol w r symbol address when reset tbiic(i=3 to 5) 0045 16 to 0047 16 xxxx0000 2 bcnic 004a 16 xxxx0000 2 dmiic(i=0, 1) 004b 16 , 004c 16 xxxx0000 2 kupic 004d 16 xxxx0000 2 adic 004e 16 xxxx0000 2 sitic(i=0 to 2) 0051 16 0053 16 , 004f 16 xxxx0000 2 siric(i=0 to 2) 0052 16 , 0054 16 , 0050 16 xxxx0000 2 taiic(i=0 to 2) 0055 16 to 0057 16 xxxx0000 2 tbiic(i=0 to 2) 005a 16 to 005c 16 xxxx0000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 (note 1) note 1: to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. for details, see the precautions for interrupts. note 2: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 (note 2) 0: selects falling edge selects rising edge 1: nothing is assigned. write "0" when writing to these bits. if read, the value is "0". nothing is assigned. write "0" when writing to these bits. if read, the value is "0".
1-41 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer interrupt enable flag (i flag) the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to ?1? enables all maskable interrupts; setting it to ?0? disables all maskable interrupts. this flag is set to ?0? after reset. interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is ac- cepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1"). interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bits, which consists of three interrupt control register bits. when an interrupt request occurs, the interrupt priority level is compared with the ipl of the cpu flag register. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to ?0? disables the interrupt. table 1.19 shows the settings of interrupt priority levels and table 1.20 shows the interrupt levels enabled, according to the contents of the ipl. the following are conditions under which an interrupt is accepted: ?interrupt enable flag (i flag) = 1 ?interrupt request bit = 1 (set by hardware) ?interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another. table 1.19. settings of interrupt priority levels table 1.20. interrupt levels enabled according to the contents of the ipl interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl
1-42 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer modifying the interrupt control register when modifying the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is a possibility of the interrupt request occurring, access the interrupt control register after the interrupt is disabled. the program examples are described below: when modifying an interrupt control register, it is recommended to use only the instructions: and, or, bclr and bset. using the "mov" or other instruction may cause an interrupt to be missed. example 1: int_switch1: fclr i :disable interrupts. and.b #00h, 0055h ;clear ta0ic int. priority level and int. request bit. nop ;four nop instructions are required when using the hold function . nop fset i ;enable interrupts. example 2: int_switch2: fclr i :disable interrupts. and.b #00h, 0055h ;clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ;dummy read. fset i ;enable interrupts. example 3: int_switch3: pushc flg ;push flag register onto stack fclr i ;diable interrupts. and.b #00h, 0055h ;clear ta0ic int. priority level and int. request bit. popc flg ;enable interrupts. the reason why two nop instructions (four using the hold function) or dummy read is inserted before fset i in examples 1 and 2, is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to the effects of the instruction queue.
1-43 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.24. interrupt response time interrupt sequence the interrupt sequence, described below, is performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruc- tion, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. the processor carries out the following in sequence after an interrupt request: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 16 . (2) saves the contents of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to ?0? (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed). (4) saves the contents of the temporary register (note) within the cpu in the stack area. (5) saves the contents of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruc- tion within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 1.24 shows the interrupt response time. instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) time from interrupt request is generated to when the instruction then under execution is completed. (b) time in which the instruction sequence is executed.
1-44 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction (without wait). time (b) is as shown in table 1.21. table 1.21. time required for executing the interrupt sequence fig. 1.25. time required for executing the interrupt sequence figure 1.25 shows the time required for executing the interrupt sequence variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 1.22 is set in the ipl. table 1.22. relationship between interrupts without interrupt priority levels and ipl note 1: add 2 cycles in the case of a dbc interrupt. add 1 cycle in the case of either an address coincidence interrupt or a single-step interrupt. note 2: if possible, locate an interrupt vector address in an even address. interrupt vector address stack pointer (sp) value 16-bit bus, without wait 8-bit bus, without wait even even 18 cycles (note 1) 20 cycles (note 1) even odd 19 cycles (note 1) 20 cycles (note 1) odd (note 2) even 19 cycles (note 1) 20 cycles (note 1) odd (note 2) odd 20 cycles (note 1) 20 cycles (note 1) 123456789 1011 12 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents interrupt information address 0000 indeterminate sp-2 sp-4 pc bclk internal address bus internal data bus interrupt sources without priority levels value set in the ipl watchdog timer, nmi 7 reset 0 other no change
1-45 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the flg register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. figure 1.26 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). figure 1.26. state of stack before and after acceptance of interrupt request address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m ? 1 m ? 2 m ? 3 m ? 4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ? 1 m ? 2 m ? 3 m ? 4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m )
1-46 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 1.27 shows the operation of the saving registers. note: when any int instruction in software number 32 to 63 is executed, the stack pointer is indicated by the u flag, otherwise, it is the interrupt stack pointer (isp) (2) stack pointer (sp) contains odd number [sp] (odd) [sp] ? 1 (even) [sp] ? 2 (odd) [sp] ? 3 (even) [sp] ? 4 (odd) [sp] ? 5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] ? 1 (odd) [sp] ? 2 (even) [sp] ? 3 (odd) [sp] ? 4 (even) [sp] ? 5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved sim ultaneously, all 16 bits (1) saved sim ultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h ) figure 1.27. operation of saving registers
1-47 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the sus- pended process resumes. return the other registers saved by software within the interrupt routine using the popm or similar instruction before executing the reit instruction. interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (check- ing whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bits. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. software interrupts are not affected by the interrupt priority. if an instruction is executed, control is distributed to the interrupt routine. figure 1.28 shows the priorities of hardware interrupts. reset > nmi > dbc > watchdog timer > peripheral i/o > single step > address match interrupt resolution circuit when two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. figure 1.29 shows the circuit that judges the interrupt priority level. figure 1.28. hardware interrupts priorities
1-48 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.29. maskable interrupts priorities (peripheral i/o interrupts) timer b2 timer b0 timer a3/int4 timer a1 timer b1 timer a4/int5 timer a2 uart1 reception uart0 reception uart2 reception/ack a-d conversion dma1 bus collision detection timer a0 uart1 transmission uart0 transmission uart2 transmission/nack key input interrupt dma0 int1 int2/si03 int0 level 0 (initial value) priority level of each interrupt high priority of peripheral i/o interrupts (if priority levels are same) timer b4 int3/si04 timer b3 timer b5 int7 low interrupt enable flag (i flag) watchdog timer reset dbc nmi interrupt request accepted address match int6
1-49 specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer under development int interrupt int0 to int7 are triggered by the edges of external inputs. the edge polarity is selected using the polarity select bit. the interrupt control registers, 0058 16 is used both as timer a3 and external interrupt int4 input control register, and 0059 16 is used both as timer a4 and as external interrupt int5 input control register. also, 005f 16 is used as both sio3 and external interrupt int2 input control register and 0044 16 is used as both sio4 and external interrupt int3 input control register. use the interrupt request cause select bits - bits 4, 5, 6 and 7 of the interrupt request cause select register 0 (address 035e 16 ) - to specify which interrupt request cause to select. when int4 is selected as an interrupt source, the input port for it can be selected by bits 0 and 1 of the interrupt source select register 0 (address 035e 16 ). similarly, when int5 is selected as an interrupt source, the input port for it can be selected by bits 2 and 3 of the interrupt source select register 0 (address 035e 16 ). after having set an interrupt request cause and interrupt input ports, be sure to set the corresponding interrupt request bit to "0" before enabling an interrupt. the interrupt control registers - 0058 16 , 0059 16 , 005f 16 , and 0044 16 - have the polarity-switching bit. be sure to set this bit to ?0? to select a timer or sio as the interrupt request cause. the external interrupt input can be generated both at the rising edge and at the falling edge by setting ?1? in the inti interrupt polarity switching bit of the interrupt request cause select register 1 (035f 16 ). to select two edges, set the polarity switching bit of the corresponding interrupt control register to ?falling edge? (?0?). when int4 input pin select bits = "11", int4 interupt polarity switching bit = "0", and polarity select bit = "1" of the int4 interrupt control register, an interrupt is generated by a rising edge on the input port when the exclusive pin is "h", as shown by "single edge, rise" in figure 1.32. when the exclusive pin is "h", interrupts can only be generated by an active transition on a single edge. the same applies to int5. figure 1.30 shows the interrupt request cause select registers. figure 1.31 shows the block diagram of int4 and int5.
1-50 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.30. interrupt request cause select register interrupt request cause select register 0 bit name fumction bit symbol w r symbol address when reset ifsr0 035e 16 00 16 ifsr00 b7 b6 b5 b4 b3 b2 b1 b0 int4 input pin select bit 0 : timer a3 1 : int4 0 : timer a4 1 : int5 0 0 : no int4 input 0 1 : p7 6 input enable 1 0 : p7 7 input enable 1 1 : p7 6 , p7 7 input enable 0 : sio4 1 : int3 interrupt request cause select bit ifsr01 ifsr02 ifsr03 ifsr04 ifsr05 ifsr06 ifsr07 0 0 : no int5 input 0 1 : p8 0 input enable 1 0 : p8 1 input enable 1 1 : p8 0 , p8 1 input enable int5 input pin select bit interrupt request cause select bit interrupt request cause select bit interrupt request cause select bit 0 : sio3 1 : int2 interrupt request cause select register 1 bit name function bit symbol w r symbol address when reset ifsr1 035f 16 00 16 ifsr10 b7 b6 b5 b4 b3 b2 b1 b0 int0 interrupt polarity swiching bit 0 : single edge 1 : both edges 0 : 1 : 0 : 1 : 0 : 1 : 0 : 1 : int1 interrupt polarity swiching bit int2 interrupt polarity swiching bit int3 interrupt polarity swiching bit int4 interrupt polarity swiching bit int5 interrupt polarity swiching bit 0 : 1 : ifsr11 ifsr12 ifsr13 ifsr14 ifsr15 ifsr16 ifsr17 int6 interrupt polarity swiching bit int7 interrupt polarity swiching bit 0 : 1 : 0 : 1 : both edges both edges both edges both edges both edges both edges both edges single edge single edge single edge single edge single edge single edge single edge
1-51 specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer under development figure 1.31. int4 and int5 block diagram figure 1.32. typical timing of interrupts int4 and int5 two edge detect two edge detect inti+1 input pin select bit interrupt request taiout/inti+1 tain/inti+1 interrupt edge interrupt edge select bit i= 3, 4 ?h? ?h? ?l? ?l? ?l? ?l? ?h? ?h? ?h? ?h? ?l? ?l? 0: falling edge 1: rising edge polarity select bit (bit4 of interrupt control register) 0: one edge 1: two edges int4, int5 interrupt polarity switching bit (bits 4, 5 of interrupt request cause select register 1)
1-52 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer nmi interrupt an nmi interrupt is generated when the input to the p8 3 /nmi pin changes from ?h? to ?l?. the nmi interrupt is a non-maskable external interrupt. the pin level can be checked in the port p8 3 register (bit 3 at address 03f0 16 ). this pin cannot be used as a normal port input. (see interrupt precautions section). key input interrupt all bits of port 6 can be used as key input interrupts. enable the interrupts using the kupic register, then set the direction register of any of p6 0 to p6 7 bits for input, and a falling edge to that port will generate a key input interrupt. a key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. figure 1.33 shows the block diagram of the key input interrupt. note that if an ?l? level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. figure 1.33. block diagram of key input interrupt interrupt control circuit key input interrupt control register (address 004d 16 ) key input interrupt request p6 7 /ki 7 p6 6 /ki 6 p6 5 /ki 5 port p6 0 -p6 7 pull-up select bit port p6 7 direction register pull-up transistor port p6 7 direction register port p6 6 direction register port p6 5 direction register pull-up transistor pull-up transistor p6 4 /ki 4 port p6 4 direction register pull-up transistor p6 0 /ki 0 port p6 0 direction register pull-up transistor two edge detect "1" "0" two edge detect "1" "0" two edge detect "1" "0" two edge detect "1" "0" two edge detect "1" "0" p6 key input enable bit
1-53 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.34 shows the key input mode register. with bits 0 and 1 of this register, it is possible to select both edges or the fall edge of the key input for p6. port p6 is set for pull-up using the pll-up control register. fig. 1.34. key input mode register key input mode register b7 b6 b5 b4 b3 b2 b1 b0 symbol kupm note : if this bit is set for ? two edges ? when the corresponding port has been the pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register bit symbol bit name function r w p6kis p6 key input select bit (note) 0 : falling edge 1 : two edges p6kie p6 key input enable bit 0 : disable 1 : enable nothing is assigned. write "0" when writing to these bits. the value is indeterminate when read. address 0126 16 when reset xxxxxx00 2 _ _ specified to have a pull up, the port is automatically pulled high intermittently by the operating subclock.
1-54 under development specifications in this manual are tentative and subject to change rev. g overview of interrupts mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the interrupt enable flag (i flag) and processor interrupt priority level (ipl). the stack value of the program counter (pc) for an address match interrupt varies depending on the instruction being executed. figure 1.35 shows the address match interrupt-related registers. figure 1.35. address match interrupt-related registers. bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function w r address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 symbol address when reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 nothing is assigned. 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) write 0 when writing to these bits. if read, the value is indeterminate. write 0 when writing to these bits. if read, the value is indeterminate.
1-55 under development specifications in this manual are tentative and subject to change rev. g interrupt precautions mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer precautions for interrupts (1) reading address 00000 16 ? when a maskable interrupt occurs, the cpu reads the interrupt information (the interrupt number and interrupt request level)from address 00000 16 in the interrupt sequence. the interrupt request bit of the interrupt written in address 00000 16 will then be set to ?0?. reading address 00000 16 by software enables the highest priority interrupt source request bit. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the stack pointers immediately after reset are initialized to 0000 16 . the stack pointers must nbe set to valid ram areas for proper operation. an interrupt occurring immediately after reset will cause a runaway condition. (3) the nmi interrupt ?the nmi interrupt can not be disabled. be sure to connect nmi pin to vcc via a pull-up resistor if unused. ? the nmi pin also serves as p8 5 , which is exclusively input. reading the contents of the p8 register allows reading the pin value. use the reading of this pin only for establishing the pin level at the time when the nmi interrupt is input. ? do not reset the cpu with the input to the nmi pin being in the ?l? state. ? do not attempt to go into stop mode with the input to the nmi pin being in the ?l? state. with the input to the nmi being in the ?l? state, the cm10 is fixed to ?0?, so attempting to go into stop mode is ignored. ? do not attempt to go into wait mode with the input to the nmi pin being in the ?l? state. with the input to the nmi pin being in the ?l? state, the cpu stops but the oscillation does not stop, so no power is saved. in this instance, the cpu is returned to the normal state by a later interrupt. ? minimum nmi pulse width is 1 bclk cycle. (4) external interrupts ? a minimum of 250ns pulse width is necessary for the signal input to pins int 0 through int 7 regardless of the cpu operation clock. ? when the polarity of the int 0 to int 7 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". figure 1.36 shows the procedure for changing the int interrupt generate factor.
1-56 under development specifications in this manual are tentative and subject to change rev. g interrupt precautions mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer ? when modifying an interrupt control register, it is recommended to use only the instructions: and, or, bclr, bset. using the "mov" or other instruction may cause an interrrupt to be missed. (5) rewrite the interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described below: figure 1.36. switching condition of int interrupt request example 1: int_switch1: fclr i :disable interrupts. and.b #00h, 0055h ;clear ta0ic int. priority level and int. request bit. nop ;four nop instructions are required when using the hold function . nop fset i ;enable interrupts. example 2: int_switch2: fclr i :disable interrupts. and.b #00h, 0055h ;clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ;dummy read. fset i ;enable interrupts. example 3: int_switch3: pushc flg ;push flag register onto stack fclr i ;diable interrupts. and.b #00h, 0055h ;clear ta0ic int. priority level and int. request bit. popc flg ;enable interrupts. the reason why two nop instructions (four using the hold function) or dummy read is inserted before fset i in examples 1 and 2, is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to the effects of the instruction queue. set the polarity select bit clear the interrupt request bit to ? 0 ? set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) clear the interrupt enable flag to ? 0 ? (disable interrupt) set the interrupt enable flag to ? 1 ? (enable interrupt)
1-57 under development specifications in this manual are tentative and subject to change rev. g watchdog timer mitsubishi microcomputers M30222 group single-chip 8-bit cmos microcomputer watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. when x in is selected for the bclk, bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). thus the watchdog timer's period can be calculated as given below. the watchdog timer's period is, however, subject to an error due to the prescaler. with x in chosen for bclk watchdog timer period = prescaler dividing ratio (16 or 128) x watchdog timer count (32768) bclk with xc in chosen for bclk watchdog timer period = prescaler dividing ratio (2) x watchdog timer count (32768) bclk for example, suppose that bclk runs at 16 mhz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 32.8 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler must be set before initializing the watch- dog timer. once initialized, the watchdog timer can only be stopped by a reset. the counter is reset to 7eee 16 by writing any value to the watchdog timer start register (address 000e 16 ). figure 1.37 shows the watchdog timer block diagram. figure 1.38 shows the watchdog timer-related registers. fig. 1.37. block diagram of watchdog timer bclk write to the watchdog timer start register (address 000e 16 ) reset watchdog timer interrupt request watchdog timer set to ? 7fff 16 ? 1/128 1/16 ? cm07 = 0 ? ? wdc7 = 1 ? ? cm07 = 0 ? ? wdc7 = 0 ? ? cm07 = 1 ? hold 1/2 prescaler
1-58 under development specifications in this manual are tentative and subject to change rev. g watchdog timer mitsubishi microcomputers M30222 group single-chip16-bit cmos microcomputer fig. 1.38. watchdog timer control and start registers watchdog timer control register (note) symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function reserved bit must always be set to ? 0 ? 0 0 note: set the desired prescale value before initializing the watchdog timer. the watchdog timer is initialized and starts counting after the first write instruction to this register after reset. writing any value to this register resets the counter to 7fff 16.
1-59 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer dmac this microcomputer has two dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. the dmac shares the same data bus with the cpu. the dmac uses a high speed cycle-stealing method because it has a higher right to use the bus than the cpu. dma transfers word (16-bit) or a byte (8-bit) data. figure 1.39 shows the block diagram of the dmac. table 1.23 shows the dmac specifications. figures 1.40 to 1.42 show the registers used by the dmac. either a write signal to the software dma request bit or an interrupt request signal is used as a dma transfer request signal. the dma transfers are not affected by the interrupt enable flag (i flag) or by the interrupt priority level and the dma transfer doesn't affect any interrupt. if the dmac is active (the dma enable bit is set to 1), data transfer starts every time a dma transfer request signal occurs. if the cycle of the occurrences of dma transfer request signals is higher than the dma transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. for details, see the description of the dma request bit. figure 1.39. block diagram of dmac data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits address bus dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented by a dma request.
1-60 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.23. dmac specifications note: dma transfers do not effect any interrupt and are not affected by the interrupt enable flag (i flag) or by any interrupt priority level. item specification number of channels 2 (cycle-stealing method) transfer memory space from any address in the 1m byte space to a fixed address from a fixed address to any address in the 1 m byte space from a fixed address to a fixed address dma-related registers (0020 16 to 003f 16 ) cannot be accessed maximum number of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (note) falling edge of int0 or int1 or both edges (int0 can be selected by dma0, int1 by dma1) timer a0 to timer a4 interrupt requests timer b0 to timer b5 interrupt requests uart0 transfer and receive interrupt requests uart1 transfer and receive interrupt requests uart2 transfer and receive interrupt requests serial i/o 3,4 interrupt requests a-d conversion interrupt requests software triggers channel priority dma0 has priority if dma0 and dma1 requests are generated simultaneously transfer unit 8 bit or 16 bit transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode single transfer mode after the transfer counter underflows, the dma enable becomes 0 and the dmac becomes inactive. repeat transfer mode after the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. the dmac remains active unless a 0 is written to the dma enable bit. dma interrupt request generation timing when an underflow occurs in the transfer counter active when the dma enable bit is set to 1 , the dma is active. when the dma is active, data transfer starts each time the dma transfer request signal occurs. inactive when the dma enable bit is set to 0 , the dmac is inactive. after the transfer counter underflows in single transfer mode. forward address pointer and reload timing for transfer counter when the dmac is enabled, the dma source pointer is loaded to the dma forward address pointer. the dma transfer load pointer is copied to the dma transfer counter at that time. writing to register registers specified for forward direction transfer are always write enabled. regis- ters specified for fixed address transfer are write enabled when the dma enable bit is 0 . reading the register can be read anytime. however, when the dma enable bit is 1 , reading the regis- ter set up as the forward register is the same as reading the value of the forward address pointer.
1-61 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.40. dmac register (1) dma0 request cause select register symbol address when reset dm0sl 03b8 16 00 16 function (note) bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bits dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. software dma request bit if software trigger is selected, a dma request is generated by setting this bit to ? 1 ? (when read, the value of this bit is always ? 0 ? ) dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int0 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 (dms=0) /two edges of int0 pin (dms=1) 0 1 1 1 : timer b0 (dms=0) timer b3 (dms=1) 1 0 0 0 : timer b1 (dms=0) timer b4 (dms=1) 1 0 0 1 : timer b2 (dms=0) timer b5 (dms=1) 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 transmit bit name dma request cause expansion bit dms 0: normal 1: dma caused by setting dsel0 to dsel3 (expanded cause) 1 : expanded cause note: when the selected functions of the interrupt request are set, a dma transfer request will occur. write "0" when writing to these bits. if read, the value is "0".
1-62 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.41. dmac register (2) dmai control register symbol address when reset dmicon(i=0,1) 002c 16 , 003c 16 xx000000 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits dmbit rw dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit (note 1) 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 3) destination address direction select bit (note 3) 0 : fixed 1 : forward dsd dad nothing is assigned. note 1: dma request can be cleared by resetting the bit. note 2: this bit can only be set to ? 0 ? . note 3: source address direction select bit and destination address direction select bit cannot be set to ? 1 ? simultaneously. (note 2) dma0 request cause select register symbol address when reset dm1sl 03ba 16 00 16 function (note) bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bits dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. software dma request bit if software trigger is selected, a dma request is generated by setting this bit to ? 1 ? (when read, the value is always ? 0 ? ) dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int1 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 (dms=0) /serial i/o4 (dms=1) 0 1 1 1 : timer b0 (dms=0) /two edges of int1 (dms=1) 1 0 0 0 : timer b1 1 0 0 1 : timer b2 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 transmit bit name dma request cause expansion bit dms 0: normal 1: dma is caused by setting dsel0 to dsel3 (expanded cause) note: when the selected functions of the interrupt request are set, a dma transfer request will occur. (dms=0) /serial i/o3 (dms=1) write "0" when writing to these bits. if read, the value is "0". write "0" when writing to these bits. if read, the value is "0".
1-63 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.42. dmac register (3) b7 b0 b7 b0 (b8) (b15) function rw transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. write "0" when writing to these bits. if read, the value is "0". write "0" when writing to these bits. if read, the value is "0".
1-64 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses. also, the bus cycle itself is longer when software waits are inserted. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination starts at odd ad- dresses, there is one more source read cycle and destination write cycle than when the source and destina- tion both start at even addresses. (b) effect of software wait when the sfr area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. the length of the cycle is determined by bclk. figure 1.43 shows the transfer cycles for a source read. for convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle.
1-65 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.43. example of the transfer cycle for a source read bclk address bus rd wr data bus cpu use cpu use cpu use cpu use source source destination destination (1) 8-bit transfers 16-bit transfers from even address and the source address is even. bclk address bus rd wr data bus cpu use cpu use cpu use cpu use source source destination destination (3) one wait is inserted into the source read under the conditions in (1) bclk address bus rd wr data bus cpu use cpu use cpu use cpu use source source destination destination source + 1 source + 1 (2) 16-bit transfers and the source address is odd bclk address bus rd wr data bus cpu use cpu use cpu use cpu use source source destination destination source + 1 source + 1 (4) one wait is inserted into the source read under the conditions in (2) note 1: the same timing changes occur with the respective conditions at the destination as at the source. note 2: this cycle may be added depending on the instruction queue. note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2
1-66 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (2) dmac transfer cycles any combination of even or odd transfer read and write addresses is possible. table 1.24 shows the number of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k internal memory sfr area 122 coefficient j, k transfer unit bus width access address no. of read cycles no. of write cycles 16-bit even 1 1 8-bit transfers (byte= ? l ? ) odd 1 1 (dmbit= ? 1 ? ) 16-bit even 11 16-bit transfers (byte = ? l ? ) odd 2 2 (dmbit= ? 0 ? ) internal rom/ram no wait internal rom/ram with wait table 1.24. no. of dmac transfer cycles
1-67 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer dma enable bit setting the dma enable bit to "1" makes the dmac active. the dmac carries out the following opera- tions at the time data transfer starts immediately after dmac is turned active. (1) reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) reloads the value of the transfer counter reload register to the transfer counter. thus overwriting "1" to the dma enable bit with the dmac being active carries out the operations given above, so the dmac operates again from the initial state at the instant "1" is overwritten to the dma enable bit. dma request bit the dma request bit is set by a dma transfer request signal. this signal is triggered by a factor selected in advance by the dami request cause select bits. dma request factors include the following: ?factors effected by using the interrupt request signals from the built-in peripheral functions and software dma factors (internal factors) effected by a program. ? external factors effected by utilizing the input from external interrupt signals. for the selection of dma request factors, see the descriptions of the dmai register. the dma request bit turns to "1" if the dma transfer request signal occurs regardless of the dmac's state (regardless of whether the dma enable bit is set "1" or to "0"). it turns to "0" immediately before data transfer starts. in addition, it can be set to "0" by use of a program, but cannot be set to "1". there can be instances in which a change in dma request factor selection bit causes the dma request bit to turn to "1". be sure to set the dma request bit to "0" after the dma request factor selection bit is changed. the dma request bit turns to "1" if a dma transfer request signal occurs, and turns to "0" immediately before data transfer starts. if the dmac is active, data transfer starts immediately, so the value of the dma request bit, if read by use of a program, turns out to be "0" in most cases. to examine whether the dmac is active, read the dma enable bit. the timing of changes in the dma request bit is explained below. (1) internal factors except the dma request factors triggered by software, the timing for the dma request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. turning the dma request bit to "1" due to an internal factor is timed to be effected immediately before the transfer starts.
1-68 under development specifications in this manual are tentative and subject to change rev. g direct memory access controller mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (2) external factors an external factor is a factor caused to occur by the leading edge of input from the inti pin (i depends on which dmac channel is used). selecting the inti pins as external factors using the dma request factor selection bit causes input from these pins to become the dma transfer request signals. the timing for the dma request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the dma request factor selection bit (synchronizes with the trailing edge of the input signal to each inti pin, for example). with an external factor selected, the dma request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected. (3) the priorities of channels and dma transfer timing if a dma transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of bclk), the dma request bits of applicable channels concurrently turn to "1". if the channels are active at that moment, dma0 is given a high priority to start data transfer. when dma0 finishes data transfer, it gives the bus right to the cpu. when the cpu finishes single bus access, then dma1 starts data transfer and gives the bus right to the cpu. figure 1.44 shows an example in which dma transfer is carried out in minimum cycles at the time when dma transfer request signals due to external factors concurrently occur. fig. 1.44. an example of dma transfer affected by external factors bclk dma0 dma1 dma0 request bit dma1 request bit cpu int0 int1 bus control example of dma transmission that is carried out in minimum cycles at the time dma transmission occur concurrently. ///////////////// ////////////// /////////// /////// ///////////
1-69 under development specifications in this manual are tentative and subject to change rev. g timers mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer timers there are eleven 16-bit timers. these timers can be classified by function into timers a (five) and timers b (six). all these timers function independently. figures 1.45 and 1.46 show the block diagram of timers. figure 1.45. timer a block diagram timer mode one-shot mode pwm mode timer mode one-shot mode pwm mode timer mode one-shot mode pwm mode timer mode one-shot mode pwm mode timer mode one-shot mode pwm mode event counter mode event counter mode event counter mode event counter mode event counter mode ta 0 in ta 1 in ta 2 in ta 3 in ta 4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 1 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to ? 1 ? reset clock prescaler timer b2 overflow note 1: the ta3 in pin (p7 7 ) is shared with int4 pin. note 2: the ta4 in pin (p8 1 ) is shared with int5 pin. port 3 real-time output trigger port 4 real-time output trigger (note 1) (note 2)
under development 1-70 specifications in this manual are tentative and subject to change rev. g timers mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.46. timer b block diagram event counter mode event counter mode event counter mode timer mode pulse width measuring mode timer mode pulse width measuring mode timer mode pulse width measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 1 f 8 f 32 f c32 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to ? 1 ? reset clock prescaler timer a event counter mode event counter mode event counter mode timer mode pulse width measuring mode timer mode pulse width measuring mode timer mode pulse width measuring mode tb3 in tb4 in tb5 in timer b3 timer b4 timer b5 timer b3 interrupt noise filter noise filter noise filter timer b1 interrupt timer b2 interrupt timer b4 interrupt timer b5 interrupt note 1: the tb0 in pin (p9 0 ) is shared with int2 pin (note 1)
under development 1-71 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer timer a figure 1.47 shows the block diagram of timer a. figures 1.48 to 1.50 show the timer a-related registers. except in event counter mode, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer over flow. ? one-shot timer mode: the timer stops counting when the count reaches ?0000 16 ?. ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. ? real-time port mode. fig. 1.47. block diagram of timer a fig. 1.48. timer a-related registers (1) count start flag (address 0380 16 ) up count/down count ta i addresses taj tak timer a0 0387 16 0386 16 timer a4 timer a1 timer a1 0389 16 0388 16 timer a0 timer a2 timer a2 038b 16 038a 16 timer a1 timer a3 timer a3 038d 16 038c 16 timer a2 timer a4 timer a4 038f 16 038e 16 timer a3 timer a0 always down count except in event counter mode reload register (16) counter (16) low-order 8 bits high-order 8 bits clock source selection timer (gate function) timer one shot pwm f 1 f 8 f 32 external trigger ta i in (i = 0 to 4) tb2 overflow event counter f c32 clock selection taj overflow (j = i ? 1. note that j = 4 when i = 0) pulse output toggle flip-flop ta i out (i = 0 to 4) data bus low-order bits data bus high-order bits up/down flag down count (address 0384 16 ) tak overflow polarity selection (k = i + 1. note that k = 0 when i = 4) timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit
under development 1-72 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.49. timer a-related registers (2) timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address when reset udf 0384 16 00 16 ta4p ta3p ta2p up/down flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled when not using the two-phase pulse signal processing function, set the select bit to ? 0 ? symbol address when reset tabsr 0380 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s symbol address when reset ta0 0387 16 ,0386 16 indeterminate ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta3 038d 16 ,038c 16 indeterminate ta4 038f 16 ,038e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (note) w r timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set event counter mode 0000 16 to ffff 16 counts pulses from an external source or timer overflow one-shot timer mode 0000 16 to ffff 16 counts a one shot width pulse width modulation mode (16-bit pwm) functions as a 16-bit pulse width modulator pulse width modulation mode (8-bit pwm) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to fe 16 (both high-order and low-order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units.
under development 1-73 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.50. timer a-related registers (3) symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ? 0 ? ) cpsr w r ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to ? 0 ? . ta1os ta2os ta0os one-shot start flag symbol address when reset onsf 0382 16 00x00000 2 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta0tgl ta0tgh 0 0 : input on ta0 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 note: set the corresponding port direction register to ? 0 ? . w r 1 : timer start when read, the value is ? 0 ? nothing is assigned. write "0" when writing to these bits. when read, the value is indeterminate. nothing is assigned. write "0" when writing to this bit. when read, the value is indeterminate.
under development 1-74 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.25.) figure 1.51 shows the timer ai mode register in timer mode. usage precautions reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ?ffff 16 ?. reading the timer ai register after setting a value in thetimer ai register with a count halted but before the counter starts counting gets a proper value. table 1.25. timer mode specifications item specification count source f1, f8, f32, fc32 count operation count down when the timer underflows, it reloads the reload register contents before count- ing continues. divide ratio 1/(n+1) n: set value count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) interrupt request generation timing when timer underflows taiin pin function programmable i/o port or gate input taiout pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer ai register write to timer when counting stops when a value is written to timer ai register, it is written to both reload register and counter when counting is in progress when a value is written to timer ai regiser, it is written to only reload register (transferred to counter at next reload time). select function gate function counting can be started and stopped by the taiin pin s input signal. pulse output function each timer the timer underflows, the taiout pin s polarity is reversed.
under development 1-75 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.51. timer ai mode register in timer mode (2) event counter mode in this mode, the timer counts an external signal or an internal timer?s overflow. timers a0 and a1 can count a single-phase external signal. timers a2, a3, and a4 can count a single-phase and a two-phase external signal. table 1.26 lists timer specifications when counting a single-phase external signal. figure 1.52 shows the timer ai mode register in event counter mode. table 1.27 lists timer specifica- tions when counting a two-phase external signal. figure 1.53 shows the timer ai mode register in event counter mode. usage precautions (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ?ffff 16 ? by underflow or ?0000 16 ? by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. note 1: the settings of the corresponding port register and port direction register are invalid. timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (ta iout pin is a pulse output pin) gate function select bit 0 x (note 2) : gate function not available (tai in pin is a normal port pin) 1 0 : timer counts only when ta iin pin is held ? l ? (note 3) 1 1 : timer counts only when ta iin pin is held ? h ? (note 3) b4 b3 mr2 mr1 mr3 0 (must always be fixed to ? 0 ? in timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 note 2: the bit can be "0" or "1". note 3: set the corresponding port direction register to "0".
under development 1-76 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.26. timer specifications in event counter mode (when not processing two-phase pulse signal) fig. 1.52. timer ai mode register in event counter mode note: this does not apply when the free-fun function is selected. item specification count source external signals input to taiin pin (effective edge can be selected by software) tb2 overflow, taj overflow count operation up count or down count can be selected by external signal or software. when the timer overflows or underflows, it reloads the reload register contents before counting continues (note) divide ratio 1/(ffff 16 - n+1) for up count 1/(n + 1) for down count n: set value count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) interrupt request generation timing the timer overflows or underflows. taiin pin function programmable i/o port or count source input taiout pin function programmable i/o port or pulse output, or up/down count select input read from timer count value can be read out by reading timer ai register write to timer when counting stops when a value is written to timer ai register, it is written to both reload register and counter when counting is in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time). select function free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it. pulse output function each timer the timer overflows or underflows, the taiout pin s polarity is reversed. timer ai mode register note 1: in event counter mode, the count source is selected by the event / trigger select bit (addresses 0382 16 and 0383 16 ). symbol address when reset taimr(i = 0, 1) 0396 16 , 0397 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 2) (ta iout pin is a pulse output pin) count polarity select bit (note 3) mr2 mr1 mr3 0 (must always be fixed to ? 0 ? in event counter mode) tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 4) 0 : reload type 1 : free-run type bit symbol bit name function tck1 invalid in event counter mode can be ? 0 ? or ? 1 ? tmod1 note 2: the settings of the corresponding port register and port direction register are invalid. note 3: valid only when counting an external signal. note 4: when an "l" signal is input to the tai out pin, the downcount is activated. when "h", the upcount is activated. set the corresponding port direction register to "0".
under development 1-77 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.27. timer specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3,and a4) tai out in (i=2,3) tai up count up count up count down count down count down count count up all edges count down all edges count up all edges count down all edges ta i in (i=3,4) ta i out item specification count source two-phase pulse signals input to tai in or tai out pin count operation up count or down count can be selected by two-phase pulse signal when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows ta i in pin function two-phase pulse input ta i out pin function two-phase pulse input read from timer count value can be read out by reading timer a2, a3, or a4 register write to timer when counting stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter when counting in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register. (transferred to counter at next reload time.) select function normal processing operation the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is ? h ? multiply-by-4 processing operation if the phase relationship is such that the tai in pin goes ? h ? when the input signal on the tai out pin is ? h ? , the timer counts up rising and falling edges on the tai out and tai in pins. if the phase relationship is such that the ta i in pin goes ? l ? when the input signal on the tai out pin is ? h ? , the timer counts down rising and falling edges on the tai out and tai in pins. note: this does not apply when the free-run function is selected
under development 1-78 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.53. timer ai mode register in event counter mode note 1: the settings of the corresponding port register and port direction register are invalid. note 2: this bit is valid when only counting an external signal. note 3: set the corresponding port direction register to ? 0 ? . note 4: this bit is valid for the timer a3 mode register. for timer a2 and a4 mode registers, this bit can be ? 0 ? or ? 1 ? . note 5: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to ? 1 ? . also, always be sure to set the event/trigger select bit (addresses 0382 16 and 0383 16 ) to ? 00 ? . timer ai mode register (when not using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (tai out pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) count polarity select bit (note 2) mr2 mr1 mr3 0 : (must always be ? 0 ? in event counter mode) tck1 tck0 01 0 0 : counts external signal's falling edges 1 : counts external signal's rising edges up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 3) bit symbol bit name function w r count operation type select bit two-phase pulse signal processing operation select bit (note 4)(note 5) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation note 1: this bit is valid for timer a3 mode register. for timer a2 and a4 mode registers, this bit can be ? 0 ? or ? 1 ? . timer ai mode register (when using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 0 (must always be ? 0 ? when using two-phase pulse signal processing) 0 (must always be ? 0 ? when using two-phase pulse signal processing) mr2 mr1 mr3 0 (must always be ? 0 ? when using two-phase pulse signal processing) tck1 tck0 01 0 1 (must always be ? 1 ? when using two-phase pulse signal processing) bit symbol bit name function w r count operation type select bit two-phase pulse processing operation select bit (note 1)(note 2) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 note 2: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to "1". always be sure to set the event/trigger select bit (address 0382 16 ) to "00".
under development 1-79 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (3) one-shot timer mode in this mode, the timer operates only once as shown in table 1.28. when a trigger occurs, the timer starts up and continues operating for a given period. figure 1.54 shows the timer ai mode register in one-shot timer mode. usage precautions (1) setting the count start flag to ?0? while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the tai out pin outputs ?l? level. ? the interrupt request generated and the timer ai interrupt request bit goes to ?1?. (2) the timer ai interrupt request bit goes to ?1? if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to usetimer ai interrupt (interrupt request bit), set timer ai interrupt request bit to ?0? after the above listed changes have been made. item specification count source f1, f8, f32, fc32 count operation timer counts down when the count reaches 0000 16 , the timer stops counting after reloading a new count. if a trigger occurs when counting, the timer reloads a new count and restarts counting. divide ratio 1/n n: set value count start condition an external trigger is input timer overflows one-shot start flag is set (=1) count stop condition a new count is reloaded after the count has reached 0000 16 the count start flag is reset (=0) interrupt request generation timing the count reaches 0000 16 taiin pin function programmable i/o port or trigger input taiout pin function programmable i/o port or pulse output read from timer when timer ai register is read, it indicates an indeterminate value. write to timer when counting stops when a value is written to timer ai register, it is written to both reload register and counter when counting is in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time). table 1.28. timer specifications in one-shot timer mode
under development 1-80 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 1.29.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 1.55 shows thetimer ai mode register in pulse width modulation mode. figure 1.56 shows the example of how a 16-bit pulse width modulator operates. figure 1.57 shows the example of how an 8-bit pulse width modulator operates. usage precautions (1) the timer ai interrupt request bit becomes ?1? if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to usetimer ai interrupt (interrupt request bit), set timer ai interrupt request bit to ?0? after the above listed changes have been made. (2) setting the count start flag to ?0? while pwm pulses are being output causes the counter to stop counting. if the tai out pin is outputting an ?h? level in this instance, the output level goes to ?l?, and the timer ai interrupt request bit goes to ?1?. if the tai out pin is outputting an ?l? level in this instance, the level does not change, and thetimer ai interrupt request bit does not becomes ?1?. fig. 1.54. timer ai mode register in one-shot timer mode bit name timer ai mode register symbol address when reset taimr(i = 0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) mr2 mr1 mr3 0 (must always be ? 0 ? in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : one-shot start flag is valid 1 : selected by event/trigger select register trigger select bit external trigger select bit (note 2) 0 : falling edge of tai in pin's input signal (note 3) 1 : rising edge of tai in pin's input signal (note 3) note 1: the settings of the corresponding port register and port direction register are invalid. note 2: valid only when the ta iin pin is selected by the event/trigger select bit (address 0382 16 w r and 0383 16 ). if timer overflow is selected, this bit can be "1" or "0". note 3: set the corresponding port direction register to "0".
under development 1-81 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.29. timer specifications in pulse width modulation mode fig. 1.55. timer ai mode register in pulse width modulation mode item specification count source f1, f8, f32, fc32 count operation timer counts down (operating as an 8-bit or 16-bit pulse modulator) timer reloads new count at a rising edge of pwm pulse and continues counting. timer is not affected by a trigger that occurs when counting. 16-bit pwm high level width n/fi n: set value cycle time (2 16 -1)/fi fixed 8-bit pwm high level width n x (m + 1)/fi n: values set timer ai s high-order address cycle time (28-1) x (m+1)/fi m: values set timer ai s low-order address count start condition external trigger is input timer overflows count start flag is set (=1) count stop condition count start flag is reset (=0) interrupt request generation timing pwm pulse goes l taiin pin function programmable i/o port or trigger input taiout pin function pulse output read from timer when timer ai register is read, it indicates an indeterminate value. write to timer when counting stops when a value is written to timer ai register, it is written to both reload register and counter. when counting is in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time). bit name timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit w r 11 1 1 (must always be ? 1 ? in pwm mode) 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) 0: falling edge of tai in pin's input signal (note 2) 1: rising edge of tai in pin's input signal (note 2) 0: count start flag is valid 1: selected by event/trigger select register note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be ? 1 ? or ? 0 ? . mr2 note 2: set the corresponding port direction register to "0".
under development 1-82 specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.56. example of how a 16-bit pulse width modulator operates fig. 1.57. example of how an 8-bit pulse width modulator operates count source (note1) ta iin pin input signal underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin ? h ? ? h ? ? h ? ? l ? ? l ? ? l ? ? 1 ? ? 0 ? timer ai interrupt request bit cleared to ? 0 ? when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of taiin pin input signal) is selected 1 / f i x (m + 1) x (2 ? 1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1) note 3: m = 00 16 to fe 16 ; n = 00 16 to fe 16 1 / f i x (2 ? 1) 16 count source ta iin pin input signal pwm pulse output from ta iout pin condition : reload register = 0003 16 , when external trigger (rising edge of ta iin pin input signal) is selected trigger is not generated by this signal ? h ? ? h ? ? l ? ? l ? timer ai interrupt request bit ? 1 ? ? 0 ? cleared to ? 0 ? when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note: n = 0000 16 to fffe 16 1 / f i x n note: n = 0000
1-83 under development specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.58. block diagram of real-time port output (5) real-time port mode when real-time port output is selected, the data previously written to the port pm latch is clocked into the real-time port latch each time the corresponding timer ai underflows. the real-time port data is written to the corresponding port pm register. when the real-time port mode select bit changes state from "0" to "1", the value of the real-time port latch becomes "0", which is ouput from the correspond- ing pin. it is when timer ai underflows first that the real-time port data is ouput. if the real-time port data is modified when the real-time port function is enabled, the modified value is output when timer ai underflows next time. the port functions as an ordinary port when the real-time port function is disabled. make sure timer ai for real-time port output is set for timer mode, and is set to have "no gate function" using the gate function select bit. also, before setting the real-time port mode select bit to "1", temporarily turn off timer ai and write its set value to the register. figure 1.58 shows the block diagram for real-time port output. figure 1.59 shows the real-time control register. figure 1.60 shows timing in real-time port output operation. timer ai mode register (address 0396 16 and 0397 16 ) 00 00 b7 b6 b5 b4 b3 b2 b1 b0 data bus data bus data bus data bus port latch port latch port latch port latch timer ai interrupt timer ai * timer mode t q d t q d t q d t q d real time port latch timer ak overflow timer ai+1 overflow noise filter timer bj overflow ta iin 2 f 1 f s f 32 f c132 j=2, k=4, 0, m=0, 1 when i=0, 1 ~ ~ ~ ~ p3 0 /rtp00 rtp0 real-time port select bit p3 1 /rtp01 p4 6 /rtp70 p4 7 /rtp71 rtp7 real-time port select bit data bus set values for real-time port used in timer ai mode register
1-84 under development specifications in this manual are tentative and subject to change rev. g timer a mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.60. timing in real-time port output operation figure 1.59. real-time port control register real-time port control register (note) symbol address when reset rtp 03ff 16 xxxx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 the corresponding ports of output is controlled 0 : ordinary port output 1 : real-time port output rtp0 rtp1 rtp2 rtp3 p3 0 , p3 1 real-time port mode select bit p3 2, p3 3 real-time port mode select bit p3 4, p3 5 real-time port mode select bit p3 6, p3 7 real-time port mode select bit note: the corresponding port direction register is invalid rtp4 rtp5 rtp6 rtp7 p4 0, p4 1 real-time port mode select bit p4 2, p4 3 real-time port mode select bit p4 4, p4 5 real-time port mode select bit p4 6, p4 7 real-time port mode select bit o o o o o o o o start count underflow underflow timer 55 16 55 16 aa 16 aa 16 counter content (hex) count start flag timer ai interrupt request bit (i=0, 1, 5, 6) real time port output writing to port pm register (m=0, 1, 2, 12) value to port pm (example) ? 1 ? ? 0 ? ? 1 ? ? 0 ? note : after a reset, the value of the real time port latch is ? 00 ? . the value of the real time port latch changes irrespective of the real time port mode select bit as the value of the port pm register is updated by an underflow of the corresponding timer ai.
under development 1-85 specifications in this manual are tentative and subject to change rev. g timer b mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer timer b figure 1.61shows the block diagram of timer b. figures 1.62 and 1.63 show the timer b-related registers. use the timer bi mode register (i= 0 to 5) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: ?timer mode: the timer counts an internal count source. ?event counter mode: the timer counts pulses from an external source or a timer overlfow. ?pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. clock source selection (address 0380 16 ) event counter timer pulse period/pulse width measurement reload register (16) low-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow j = i ? 1. note, however, can be selected in only event counter mode count start flag f c32 polarity switching and edge pulse tbi in (i = 0 to 5) counter reset circuit counter (16) tbi address tbj timer b0 0391 16 0390 16 timer b2 timer b1 0393 0392 timer b0 j = 2 when i = 0 j = 5 when i = 3 timer b2 0395 16 0394 16 timer b1 timer b3 0351 16 0350 16 timer b5 timer b4 0353 16 0352 16 timer b3 timer b5 0355 16 0354 16 timer b4 16 16 high-order 8-bits timer bi mode register symbol address when reset tbimr(i = 0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : inhibited b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit (note 1) (note 2) note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. fig. 1.62. timer b-related registers (1) fig. 1.61. block diagram of timer b
under development 1-86 specifications in this manual are tentative and subject to change rev. g timer b mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer symbol address when reset tabsr 0380 16 00 16 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ? 0 ? ) cpsr symbol address when reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate tb3 0351 16 , 0350 16 indeterminate tb4 0353 16 , 0352 16 indeterminate tb5 0355 16 , 0354 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r pulse period / pulse width measurement mode measures a pulse period or width timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow note: read and write data in 16-bit units. symbol address when reset tbsr 0340 16 timer b3, 4, 5 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b5 count start flag timer b4 count start flag timer b3 count start flag 0 : stops counting 1 : starts counting tb5s tb4s tb3s function 000xxxxx 2 nothing is assigned. write "0" when writing to these bits. when read, the value is "0". nothing is assigned. write "0" when writing to these bits. when read, the value is "0". fig. 1.63. timer b-related registers (2)
under development 1-87 specifications in this manual are tentative and subject to change rev. g timer b mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.30). figure 1.64 shows the timer bi mode register in timer mode. usage precaution reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ?ffff 16 ?. reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value. table 1.30. timer mode specifications count source count operation divide ratio count start condition count stop condition interrupt request generation timing tbi in pin function read from timer write to timer f1, f8, f32, fc32 count down when the timer underflows, it reloads the reload register contents before continuous counting 1/(n+1) n: set value count start flag is set (=1) count start is reset (=0) when the timer underflows programmable i/o port or gate input count value can be read out by reading timer bi register when counting stopped w hen a value is written to timer bi register, it is written to both reload register and counter when the timer underflows, it reloads the reload register contents before continuous counting when a value is written to timer bi register,it is written to only reload register (transferred to counter at item specification next reload time)
under development 1-88 specifications in this manual are tentative and subject to change rev. g timer b mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table 1.31). figure 1.65. shows the timer bi mode register in event counter mode. usage precaution reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ?ffff 16 ?. reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value fig. 1.64. timer bi mode register in timer mode note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be ? 0 ? or ? 1 ? mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. 0 0 (fixed to ? 0 ? in timer mode ; i = 0, 3) (note 1) (note 2) b7 b6 nothing is assigned (i=1, 2, 4, 5) write "0" when writing to this bit. if read, the value is indeterminate. write "0" when writing to this bit. if read in timer mode, the value is indeterminate.
under development 1-89 specifications in this manual are tentative and subject to change rev. g timer b mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.65. timer bi mode register in event counter mode table 1.31. timer specifications in event counter mode item specification count source ? external signals input to tbiin pin ? effective edge of count source can be a rising edge or falling edge or both as selected by software count operation ? count down ? when the timer underflows, it reloads the reload register content before conti- nous counting. divide ratio 1/(n + 1) n: set value count start condition count start flag is set (=i) count stop condition count start flag is reset (=0) interrupt request generation timing the timer underflows. tbiin pin function count source input read from timer count value can be read out by reading timer bi register write to timer ? when counting stops when a value is written to timer bi register, it is written to both reload register and counter. ? when counting is in progress when a value is written to timer bi register, it is written to only reload register. (transferred to counter at next reload time). timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 invalid in event counter mode. in an attempt to write to this bit, write ? 0 ? . if read, the value in event counter mode, is indeterminate. tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : inhibited b3 b2 nothing is assigned (i = 1, 2, 4, 5). note 1: valid only when input from the tbi in pin is selected as the event clock. if timer's overflow is selected, this bit can be ? 0 ? or ? 1 ? . note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. note 4: set the corresponding port direction register to ? 0 ? . invalid in event counter mode. can be ? 0 ? or ? 1 ? . event clock select 0 : input from tbi in pin (note 4) 1 : tbj overflow (j = i ? 1; however, j = 2 when i = 0, j = 5 when i = 3) 0 (fixed to ? 0 ? in event counter mode; i = 0, 3) (note 2) (note 3) write "0" when writing to this bit. if read, the value is indeterminate.
under development 1-90 specifications in this manual are tentative and subject to change rev. g timer b mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 1.32). figure 1.66 shows the timer bi mode register in pulse period/pulse width measurement mode. figure 1.67 shows the operation timing when measuring a pulse period. figure 1.68 shows the operation timing when measuring a pulse width. usage precautions (1) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to ?1?. (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. note 1: an interrupt requst is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input. item specification count source f1, f8, f32, fc32 count operation count up counter value 0000 16 is transferred to reload register at measurement pulse s effec- tive edge and the timer continues counting. count start condition count start flag is set (=1) count stop condition count start flag is reset (=0) interrupt request generation timing when measurement pulse s effective edge is input (note 1) when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1 . the timer bi overlfow changes to 0 when the count start flag is 1 and the value is written to another timer bi timer mode register). tbiin pin function measurement pulse input read from timer when timer bi register is read, it indicates the reload register s content (measurement result) (note 2) write to timer cannot write to timer table 1.32. timer specifications in pulse period/pulse width measurement mode
under development 1-91 specifications in this manual are tentative and subject to change rev. g timer b mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.66. timer bi mode register in pulse period/pulse width measurement mode timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (interval between measurement pulse's falling edge to falling edge) 0 1 : pulse period measurement (interval between measurement pulse's rising edge to rising edge) 1 0 : pulse width measurement (interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : inhibited function b3 b2 count source select bit timer bi overflow flag ( note 1) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note 1: the timer bi overflow flag changes to ? 0 ? when the count start flag is ? 1 ? and a value is written to the timer bi mode register. this flag cannot be set to ? 1 ? by software. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. 0 (fixed to ? 0 ? in pulse period/pulse width measurement mode; i = 0, 3) (note 2) (note 3) nothing is assigned. ( i= 1, 2, 4, 5) write "0" when writing to this bit. if read, the value is indeterminate. count source measurement pulse count start flag timer bi interrupt request bit timing at which counter reaches ? 0000 16 ? ? h ? ? 1 ? transfer (indeterminate value) ? l ? ? 0 ? ? 0 ? timer bi overflow flag ? 1 ? ? 0 ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 2) cleared to ? 0 ? when interrupt request is accepted, or cleared by software. transfer (measured value) ? 1 ? reload register counter transfer timing fig. 1.67. operation timing when measuring a pulse period
under development 1-92 specifications in this manual are tentative and subject to change rev. g timer b mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.68. operation timing when measuring a pulse width measurement pulse ? h ? count source count start flag timer bi interrupt request bit timing at which counter reaches ? 0000 16 ? ? 1 ? ? 1 ? transfer (measured value) transfer (measured value) ? l ? ? 0 ? ? 0 ? timer bi overflow flag ? 1 ? ? 0 ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to ? 0 ? when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing
under development 1-93 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer timer functions for three-phase motor control use of more than one built-in timer a and timer b provides the means of outputting three-phase motor driving waveforms. figures 1.69 to 1.71 show registers related to timers for three-phase motor control. fig. 1.69. registers related to timers for three-phase motor control three-phase pwm control register 0 symbol address when reset invc0 0348 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 effective interrupt output polarity select bit (note 4) inv00 bit symbol bit name description rw inv01 effective interrupt output specification bit (note4) inv02 mode select bit (note 2) inv04 positive and negative phases concurrent l output disable function enable bit inv07 software trigger bit inv06 modulation mode select bit (note 3) inv05 positive and negative phases concurrent l output detect flag inv03 output control bit 0: a timer b2 interrupt occurs when the timer a1 reload control signal is ? 1 ? . 1: a timer b2 interrupt occurs when the timer a1 reload control signal is ? 0 ? . effective only in three-phase mode 1 0: not specified. 1: selected by the effective interrupt output polarity selection bit. effective only in three-phase mode 1 0: normal mode 1: three-phase pwm output mode 0: output disabled 1: output enabled 0: feature disabled 1: feature enabled 0: not detected yet 1: already detected 0: triangular wave modulation mode 1: sawtooth wave modulation mode 1: trigger generated the value, when read, is ? 0 ? . (note 1) note 1: note 2: note 3: note 4: no value other than ? 0 ? can be written. selecting three-phase pwm output mode causes p8 0 , p8 1 , and p7 2 through p7 5 to output u, u, v, v, w, and w, and works the timer for setting short circuit prevention time, the u, v, w phase output control circuits, and the circuit for setting timer b2 interrupt frequency. in triangular wave modulation mode: the short circuit prevention timer starts in synchronization with the falling edge of timer ai output. the data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchroniz ation with the transfer trigger signal after writing to the three-phase output buffer register. in sawtooth wave modulation mode: the short circuit prevention timer starts in synchronization with the falling edge of timer a output and with the transfer trig ger signal the data transfer from the three-phase output buffer register to the three-phase output shift register is made with respect to every transfer trigger. to write ? 1 ? both to bit 0 (inv00) and bit 1 (inv01) of the three-phase pwm control register, set in advance the content of the timer b2 interrupt occurrences frequency set counter. t hree-phase pwm control register 1 symbol address when reset invc1 0349 16 00 16 bit name description bit symbol w r inv10 inv11 inv12 timer ai start trigger signal select bit timer a1-1, a2-1, a4-1 control bit short circuit timer count source select bit 0: timer b2 overflow signal 1: timer b2 overflow signal, signal for writing to timer b2 0: three-phase mode 0 1: three-phase mode 1 0 : not to be used 1 : f 1 /2 b7 b6 b5 b4 b3 b2 b1 b0 reserved bit always set to ? 0 ? 0 note 1: to use three-phase pwm output mode, write ? 1 ? to inv12. nothing is assigned. write "0" when writing to this bit. if read, the value is "0". nothing is assigned. write "0" when writing to these bits. if read, the value is "0".
under development 1-94 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.70. registers related to timers for three-phase motor control three-phase output buffer register 0 symbol address when reset idb0 034a 16 3f 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 du0 dub0 dv0 dw0 dvb0 dwb0 u phase output buffer 0 setting in u phase output buffer 0 v phase output buffer 0 w phase output buffer 0 u phase output buffer 0 v phase output buffer 0 w phase output buffer 0 setting in v phase output buffer 0 setting in w phase output buffer 0 setting in w phase output buffer 0 setting in v phase output buffer 0 setting in u phase output buffer 0 three-phase output buffer register 1 symbol address when reset idb1 034b 16 3f 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 du1 dub1 dv1 dw1 dvb1 dwb1 u phase output buffer 1 setting in u phase output buffer 1 v phase output buffer 1 w phase output buffer 1 u phase output buffer 1 v phase output buffer 1 w phase output buffer 1 setting in v phase output buffer 1 setting in w phase output buffer 1 setting in w phase output buffer 1 setting in v phase output buffer 1 setting in u phase output buffer 1 dead time timer symbol address when reset dtt 034c 16 indeterminate function values that can be set w r b7 b0 set dead time timer 1 to 255 timer b2 interrupt occurrences frequency set counter symbol address when reset ictb2 034d 16 indeterminate function values that can be set w r b3 b0 set occurrence frequency of timer b2 interrupt request 1 to 15 note: when executing read instruction of this register, the contents of three-phase shift register is read out. note: when executing read instruction of this register, the contents of three-phase shift register is read out. note1: in setting 1 to bit 1 (inv01) - the effective interrupt output specification bit - of three- phase pwm control register 0, do not change the b2 interrupt occurrences frequency set counter to deal with the timer function for three-phase motor control. note 2: do not write at the timing of an overflow occurrence in timer b2 nothing is assigned. write "0" when writing to these bits. if read, the value is "0". nothing is assigned. write "0" when writing to these bits. if read, the value is "0".
under development 1-95 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.71. registers related to timers for three-phase motor control symbol address when reset ta11 0343 16 ,0342 16 indeterminate ta21 0345 16 ,0344 16 indeterminate ta41 0347 16 ,0346 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r counts an internal count source 0000 16 to ffff 16 function values that can be set timer ai-1 register (note) note: read and write data in 16-bit units. symbol address when reset ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta4 038f 16 ,038e 16 indeterminate tb2 0395 16 ,0394 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set one-shot timer mode 0000 16 to ffff 16 counts a one shot width note: read and write data in 16-bit units. timer ai register (note) ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to ? 0 ? . b7 b6 b5 b4 b3 b2 b1 symbol address when reset tabsr 0380 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s 1 : starts counting
under development 1-96 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.72. timer mode registers in three-phase waveform mode three-phase motor driving waveform output mode (three-phase waveform mode) setting ?1? in the mode select bit (bit 2 at 0348 16 ) shown in figure 1.69, causes three-phase waveform mode that uses four timers a1, a2, a4, and b2 to be selected. as shown in figure 1.72, set timers a1, a2, and a4 in one-shot timer mode, set the trigger in timer b2, and settimer b2 in timer mode using the respective timer mode registers. bit name timer ai mode register symbol address when reset ta1mr 0397 16 00 16 ta2mr 0398 16 00 16 ta3mr 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 (must always be ? 0 ? in three-phase pwm output mode) mr2 mr1 mr3 0 (must always be ? 0 ? in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 1 : selected by event/trigger select register trigger select bit external trigger select bit w r timer b2 mode register symbol address when reset tb2mr 039d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be ? 0 ? or ? 1 ? mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. 0 0 (fixed to ? 0 ? in timer mode ; i = 0) b7 b6 1 0 invalid in three-phase pwm output mode
under development 1-97 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.73 shows the block diagram for three-phase waveform mode. in three-phase waveform mode, the positive-phase waveforms (u phase, v phase, and w phase) and negative waveforms (u phase, v phase, and w phase), six waveforms in total, are output from p8 0 , p8 1 , p7 2 , p7 3 , p7 4 , and p7 5 as active on the ?l? level. of the timers used in this mode, timer a4 controls the u phase and u phase, timer a1 controls the v phase and v phase, and timer a2 controls the w phase and w phase respectively; timer b2 controls the periods of one-shot pulse output from timers a4, a1, and a2. in outputting a waveform, dead time can be set so as to cause the ?l? level of the positive waveform output (u phase, v phase, and w phase) not to lap over the ?l? level of the negative waveform output (u phase, v phase, and w phase). to set the dead time, use three 8-bit timers sharing the reload register. a value from 1 through 255 can be set as the count of the timer for setting dead time. the timer for setting dead time works as a one-shot timer. if a value is written to the timer (034c 16 ), the value is written to the reload register shared by the three timers for setting dead time. any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 0349 16 ). the timer can receive another trigger again before the count from the previous trigger is completed. in this instance, the timer re- loads the reload register's contents aand starts the down count again. because the timer for setting dead time works as a one-shot timer, it starts outputting pulses if trig- gered; it stops outputting pulses as soon as its content becomes 00 16 , and waits for the next trigger. the positive waveforms (u phase, v phase, and w phase) and the negative waveforms (u phase, v phase, and w phase) in three-phase waveform mode are output from respective ports by means of setting ?1? in the output control bit (bit 3 at 0348 16 ). setting ?0? in this bit causes the ports to return to a general purpose i/o port. this bit can be set to ?0? by use of the applicable instruction, entering a falling edge in the nmi terminal, or by resetting. also, if ?1? is set in the positive and negative phases concurrently, the l output disable function enable bit (bit 4 at 0348 16 ) causes one of the pairs of u phase and u phase, v phase and v phase, and w phase and w phase to go to ?l?. as a result, the port becomes the state set by the port direction register.
under development 1-98 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.73. block diagram for three-phase waveform mode timer b2 (timer mode) overflow interrupt occurrence frequency set counter interrupt request bit u(p8 0 ) u(p8 1 ) v(p7 2 ) v(p7 3 ) w(p7 4 ) w(p7 5 ) nmi reset r d d t q d t q d t q d t q for short circuit prevention d t q d t q q inv03 inv05 diagram for switching to p8 0 , p8 1 , and to p7 2 - p7 5 is not shown. inv04 timer a4 counter (one-shot timer mode) (one-shot timer mode) (one-shot timer mode) trigger timer a4 reload timer a4-1 timer a1 counter trigger timer a1 reload timer a1-1 timer a2 counter trigger timer a2 reload timer a2-1 inv0 7 t q inv11 dead time timer setting (8) inv00 1 0 inv01 inv11 du0 du1 t dq t dq dub0 dub1 t dq t dq u phase output control circuit u phase output signal u phase output signal v phase output control circuit to be set to ? 0 ? when timer a4 stops t q inv11 to be set to ? 0 ? when timer a1 stops t q inv11 to be set to ? 0 ? when timer a2 stops u phase output control circuit v phase output signal w phase output signal v phase output signal w phase output signal signal to be written to b2 trigger signal for timer ai start trigger signal for transfer inv10 circuit foriinterrupt occurrence frequency set counter bit 0 at 034b 16 bit 0 at 034a 16 three-phase output shift register (u phase) control signal for timer a4 reload f 1 inv12 1 1/2 n = 1 to 15 reload register n = 1 to 255 dead time timer setting n = 1 to 255 dead time timer setting (8) n = 1 to 255 n = 1 to 255 trigger inv06 trigger trigger trigger trigger trigger inv06 inv06 (note) note: to use three-phase output mode, write "1" to inv12
under development 1-99 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer delta modulation to generate a pwm waveform of triangular wave modulation, set ?0? in the modulation mode select bit (bit 6 at 0348 16 ). also, set ?1? in the timers a4-1, a1-1, a2-1 control bit (bit 1 at 0349 16 ). in this mode, each of timers a4, a1, and a2 has two timer registers, and alternately reloads the timer register?s content to the counter every time timer b2 counter?s content becomes 0000 16 . if ?1? is set to the effective interrupt output specification bit (bit 1 at 0348 16 ), the frequency of interrupt requests that occur every time the timer b2 counter?s value becomes 0000 16 can be set by use of the timer b2 counter (034d 16 ) . the frequency of occurrences is dependent on the reload value of timer b2. the reload value cannot be "0". setting ?1? in the effective interrupt output specification bit (bit 1 at 0348 16 ) provides the means to choose which value of the timer a1 reload control signal to use, ?0? or ?1?, to cause timer b2?s interrupt request to occur. to make this selection, use the effective interrupt output polarity selection bit (bit 0 at 0348 16 ). an example of u phase waveform is shown in figure 1.74, and the description of waveform output workings is given below. set ?1? in du0 (bit 0 at 034a 16 ). and set ?0? in dub0 (bit 1 at 034a 16 ). in addition, set ?0? in du1 (bit 0 at 034b 16 ) and set ?1? in dub1 (bit 1 at 034b 16 ). also, set ?0? in the effective interrupt output specification bit (bit 1 at 0348 16 ) to set a value in the timer b2 interrupt occurrence frequency set counter. by this setting, a timer b2 interrupt occurs when the timer b2 counter?s content becomes 0000 16 as many as (setting) times. furthermore, set ?1? in the effective interrupt output specification bit (bit 1 at 0348 16 ), set in the effective interrupt polarity select bit (bit 0 at 0348 16 ) and set "1" in the interrupt occurrence frequency set counter (034d16). these settings cause a timer b2 interrupt to occur every other interval when the u phase output goes to ?h?. when the timer b2 counter?s content becomes 0000 16 , timer a4 starts outputting one-shot pulses. in this instance, the content of du1 (bit 0 at 034b 16 ) and that of du0 (bit 0 at 034a 16 ) are set in the three- phase output shift register (u phase), the content of dub1 (bit 1 at 034b 16 ) and that of dub0 (bit 1 at 034a 16 ) are set in the three-phase shift register (u phase). after triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer b2 counter?s content becomes 0000 16 . the value of du0 and that of dub0 are output to the u terminal (p8 0 ) and to the u terminal (p8 1 ) respectively. when the timer a4 counter counts the value written to timer a4 (038f 16 , 038e 16 ) and when timer a4 finishes outputting one-shot pulses, the three-phase shift register?s content is shifted one position, and the value of du1 and that of dub1 are output to the u phase output signal and to u phase output signal respectively. at this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the ?l? level of the u phase waveform does not lap over the ?l? level of the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the ?h? level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register?s content changes from ?1? to ?0? by the effect of the one-shot pulses. when the timer for setting dead time
under development 1-100 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer finishes outputting one-shot pulses, "0" already shifted in the three-phase shift register goes effective, and the u phase waveform changes to the "l" level. when the timer b2 counter?s content becomes 0000 16 , the timer a4 counter starts counting the value written to timer a4-1 (0347 16 , 0346 16 ), and starts outputting one-shot pulses. when timer a4 finishes outputting one-shot pulses, the three- phase shift register?s content is shifted one position, but if the three-phase output shift register?s con- tent changes from ?0? to ?1? as a result of the shift, the output level changes from ?l? to ?h? without waiting for the timer for setting dead time to finish outputting one-shot pulses. a u phase waveform is generated by these workings repeatedly. with the exception that the three-phase output shift register on the u phase side is used, the workings in generating a u phase waveform, which has the opposite phase of the u phase waveform, are the same as in generating a u phase waveform. in this way, a waveform can be picked up from the applicable terminal in a manner in which the "l" level of the u phase waveform doesn?t lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the ?l? level too can be adjusted by varying the values of timer b2, timer a4, and timer a4-1. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with the u and u phases to generate an intended waveform. fig. 1.74. timing chart operation (1) timer a4 output trigger signal for timer ai start (timer b2 overflow signal) timer b2 u phase dead time a carrier wave of triangular waveform carrier wave signal wave timer b2 interrupt occurs rewriting timer a4 and timer a4-1. possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit u phase output signal mn nmpo note: set to triangular wave modulation mode and to three-phase mode 1. control signal for timer a4 reload m the three-phase shift register shifts in synchronization with the falling edge of the a4 output. u phase u phase output signal
under development 1-101 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer assigning certain values to du0 (bit 0 at 034a 16 ) and dub0 (bit 1 at 034a 16 ), and to du1 (bit 0 at 034b 16 ) and dub1 (bit 1 at 034b 16 ) allows the user to output the waveforms as shown in figure 1.75, that is, to output the u phase alone, to fix u phase to ?h?, to fix the u phase to ?h,? or to output the u phase alone. fig. 1.75. timing chart of operation (2) timer a4 output trigger signal for timer ai start (timer b2 overflow signal) timer b2 u phase dead time a carrier wave of triangular waveform carrier wave signal wave rewriting timer a4 every timer b2 interrupt occurres. u phase output signal mn nmpo note: set to triangular wave modulation mode and to three-phase mode 0. control signal for tmer a4 reload m u phase u phase output signal timer b2 interrupt occurres. rewriting three-phase buffer register.
under development 1-102 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer sawtooth modulation to generate a pwm waveform of sawtooth wave modulation, set ?1? in the modulation mode select bit (bit 6 at 0348 16 ). also, set ?0? in the timers a4-1, a1-1, and a2-1 control bit (bit 1 at 0349 16 ). in this mode, the timer registers of timers a4, a1, and a2 comprise conventional timers a4, a1, and a2 alone, and reload the corresponding timer register?s content to the counter every time the timer b2 counter?s content becomes 0000 16 . the effective interrupt output specification bit (bit 1 at 0348 16 ) and the effective interrupt output polarity select bit (bit 0 at 0348 16 ) go nullified. an example of u phase waveform is shown in figure 1.76, and the description of waveform output workings is given below. set ?1? in du0 (bit 0 at 034a 16 ), and set ?0? in dub0 (bit 1 at 034a 16 ). in addition, set ?0? in du1 (bit 0 at 034a 16 ) and set ?1? in dub1 (bit 1 at 034a 16 ). when the timer b2 counter?s content becomes 0000 16 , timer b2 generates an interrupt, and timer a4 starts outputting one-shot pulses at the same time. in this instance, the contents of the three-phase buffer registers du1 and du0 are set in the three-phase output shift register (u phase), and the contents of dub1 and dub0 are set in the three-phase output register (u phase). after this, the three- phase buffer register?s content is set in the three-phase shift register every time the timer b2 counter?s content becomes 0000 16 . the value of du0 and that of dub0 are output to the u terminal (p8 0 ) and to the u terminal (p8 1 ) respectively. when the timer a4 counter counts the value written to timer a4 (038f 16 , 038e 16 ) and when timer a4 finishes outputting one-shot pulses, the three-phase output shift register?s content is shifted one position, and the value of du1 and that of dub1 are output to the u phase output signal and to the u output signal respectively. at this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the ?l? level of the u phase waveform doesn?t lap over the ?l? level of the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the ?h? level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register?s content changes from ?1? to ?0 ?by the effect of the one-shot pulses. when the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the u phase waveform changes to the ?l? level. when the timer b2 counter?s content becomes 0000 16 , the contents of the three-phase buffer registers du1 and du0 are set in the three-phase shift register (u phase), and the contents of dub1 and dub0 are set in the three-phase shift register (u phase) again. a u phase waveform is generated by these workings repeatedly. with the exception that the three- phase output shift register on the u phase side is used, the workings in generating a u phase wave- form, which has the opposite phase of the u phase waveform, are the same as in generating a u phase waveform. in this way, a waveform can be picked up from the applicable terminal in a manner in which the ?l? level of the u phase waveform doesn?t lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the ?l? level too can be adjusted by varying the values of timer b2 and timer a4. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with the u and u phases to generate an intended waveform. setting ?1? both in dub0 and in dub1 provides a means to output the u phase alone and to fix the u phase output to ?h? as shown in figure 1.77.
under development 1-103 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.76. timing chart of operation (3) timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform m n o p note: set to sawtooth modulation mode and to three-phase mode 0. interrupt occurres. rewriting the value of timer a4. u phase output signal u phase output signal the three-phase shift register shifts in synchronization with the falling edge of timer a4. data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer b overflow. trigger signal for timer ai start (timer b2 overflow signal)
under development 1-104 specifications in this manual are tentative and subject to change rev. g timer functions for three-phase motor control mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.77. timing chart of operation (4) timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform mn p note: set to sawtooth modulation mode and to three-phase mode 0. u phase output signal u phase output signal the three-phase shift register shifts in synchronization with the falling edge of timer a4. trigger signal for timer ai start (timer b2 overflow signal) interrupt occurres. rewriting the value of timer a4. rewriting three-phase output buffer register data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer b overflow. interrupt occurres. rewriting the value of timer a4.
1-105 under development specifications in this manual are tentative and subject to change rev. g serial communications mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer serial communications the five channels of serial communication that are available are: uart0, uart1, uart2, si/o3 and si/o4. uart0 to 2 uart0, uart1 and uart2 have exclusive timers to generate the transfer clock, so each operates independently from the others. uarti (i = 0 to 2) has two operation modes: a clock synchronous serial i/o mode and a clock asynchro- nous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 , 03a8 16 and 0378 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. uart0 through uart2 are almost equal in their functions with minor exceptions. uart2 is compliant with the subscriber identity module (sim) interface with some extra settings added in clock-asynchro- nous serial i/o mode. it also has the bus collision detection function that generates an interrupt request if the txd pin and the rxd pin are different in level. uart2 also provides support for both i 2 c and spi transfer formats. figure 1.78 shows the block diagram of uart0, uart1 and uart2. figures 1.79 and 1.80 show the block diagram of the transmit/receive unit. figures 1.81 to 1.86 show the registers related to uarti. table 1.33 shows the comparison of functions of uart0 through uart2. table 1.33. comparison of functions of uart0 through uart2 note 1: only in clock synchronous serial i/o mode. note 2: only in clock synchronous serial i/o mode and 8-bit uart mode. note 3: only in uart mode. note 4: using sim interface. note 5: input and output when using sim interface for uart2 only. function uart0 uart1 uart2 clk polarity selection supported (note 1) supported (note 1) supported (note 1) lsb first/msb first selection supported (note 1) supported (note 1) supported (note 2) continuous receive mode selection supported (note 1) supported (note 1) supported (note 1) transfer clock output from multiple pins selection not supported supported (note 1) not supported separate cts/rts pins supported not supported not supported serial data logic switch not supported not supported supported (note 4) sleep mode selection supported (note 3) supported (note 3) not supported txd, rxd i/o polarity switch not supported not supported supported txd, rxd port output format cmos or n-channel open drain cmos or n-channel open drain n-channel open drain output (note 5) parity error signal output not supported not supported supported (note 4) bus collision detection not supported not supported supported i 2 c not supported not supported supported spi not supported not supported supported
1-106 under development specifications in this manual are tentative and subject to change rev. g serial communications mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.78. block diagram of uarti (i= 0 to 2) n0 : values set to uart0 bit rate generator (brg0) n1 : values set to uart1 bit rate generator (brg1) n2 : values set to uart2 bit rate generator (brg2) rxd 2 reception control circuit transmission control circuit 1 / (n 2 +1) 1/16 1/16 1/2 bit rate generator (address 0379 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 2 cts 2 / rts 2 f 1 f 8 f 32 vcc rts 2 cts 2 txd 2 (uart2) rxd polarity reversing circuit txd polarity reversing circuit rxd 0 1 / (n 0 +1) 1/2 bit rate generator (address 03a1 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 0 clock source selection cts 0 / rts 0 f 1 f 8 f 32 reception control circuit transmission control circuit internal external vcc rts 0 cts 0 txd 0 transmit/ receive unit rxd 1 1 / (n 1 +1) 1/16 1/16 1/2 bit rate generator (address 03a9 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 1 clock source selection f 1 f 8 f 32 reception control circuit transmission control circuit internal external rts 1 cts 1 txd 1 (uart1) (uart0) clk polarity reversing circuit clk polarity reversing circuit cts/rts disabled cts/rts separated clock output pin select switch cts 1 / rts 1 / cts 0 / clks 1 cts/rts disabled cts0 from uart1 cts/rts selected cts/rts disabled v cc cts0 to uart0 cts 0 cts/rts disabled cts/rts separated cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit transmit/ receive unit 1/16 1/16
1-107 under development specifications in this manual are tentative and subject to change rev. g serial communications mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.80. block diagram of uart2 transmit/receive unit fig. 1.79. block diagram of uarti (i = 0,1) transmit/receive unit sp sp pa r 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp pa r ? 0 ? sp sp pa r 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd2 uart2 transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2 transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer register uart2 receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd2 uart (8 bits) uart (9 bits) address 037e 16 address 037f 16 address 037a 16 address 037b 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp pa r ? 0 ? reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit par: parity bit
1-108 under development specifications in this manual are tentative and subject to change rev. g serial communications mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer ? fig. 1.81. serial i/o related register (1) b7 uarti bit rate generator b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate u2brg 0379 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data nothing is assigned. in an attempt to write to these bits, write ? 0 ? . the value, if read, turn out to be indeterminate. symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate u2tb 037b 16 , 037a 16 indeterminate w r (b15) symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate u2rb 037f 16 , 037e 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol note 1: bits 15 through 12 are set to ? 0 ? when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 03a8 16 and 0378 16 ) are set to ? 000 2 ? or the receive enable bit is set to ? 0 ? . (bit 15 is set to ? 0 ? when bits 14 to 12 all are set to ? 0 ? .) bits 14 and 13 are also set to ? 0 ? when the lower byte of the uarti receive buffer register (addresses 03a6 16 , 03ae 16 and 037e 16 ) is read out. note 2: arbitration lost detecting flag is allocated to u2rb and only ? 0 ? may be written. nothing is assigned in bit 11 of u0rb and u1rb. these bits can neither be set or reset. when read, the value of this bit is ? 0 ? . receive data w r receive data 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found invalid invalid invalid oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found abt arbitration lost detecting flag (note 2) 0 : not detected 1 : detected o nothing is assigned. invalid o o invalid note 3: mode fault flag is allocated to u2rb only. nothing is assigned in bit 10 of u0rb and u1rb. the bit is read only. after mdflt is set, it can be reset only by exiting spi mdoe. mdflt spi mode fault flag (note 3) 0 : not detected 1 : detected write "0" when writing to this bit. if read, the value is "0".
1-109 under development specifications in this manual are tentative and subject to change rev. g serial communications mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.82. serial i/o related registers (2) uarti transmit/receive mode register symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye slep parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit sleep select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 1 ? 0 : odd parity 1 : even parity invalid invalid must always be ? 0 ? function (during uart mode) function (during clock synchronous serial i/o mode) uart2 transmit/receive mode register symbol address when reset u2mr 0378 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 0 1 : spi mode (note) 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse usually set to ? 0 ? 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 invalid valid when bit 6 = ? 1 ? 0 : odd parity 1 : even parity invalid invalid 0 : no reverse 1 : reverse usually set to ? 0 ? function (during uart mode) function (during clock synchronous serial i/o mode) note: bit 2 to bit 0 are set to ? 010 2 ? when i 2 c or spi mode are used. must always be ? 0 ? 0 1 0 : i 2 c mode (note)
1-110 under development specifications in this manual are tentative and subject to change rev. g serial communications mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.83. serial i/o-related registers (3) uarti transmit/receive control register 0 symbol address when reset uic0(i=0,1) 03a4 16 , 03ac 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = ? 0 ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = ? 0 ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be ? 0 ? bit name bit symbol must always be ? 0 ? note 1: set the corresponding port direction register to ? 0 ? . note 2: the settings of the corresponding port register and port direction register are invalid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) uart2 transmit/receive control register 0 symbol address when reset u2c0 037c 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge for spi, clock is high between transfers 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge for spi, clock is low between transfers clk polarity select bit cts/rts function select bit cts/rts disable bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = ? 0 ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = ? 0 ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) must always be ? 0 ? bit name bit symbol note 1: set the corresponding port direction register to ? 0 ? . note 2: the settings of the corresponding port register and port direction register are invalid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) nothing is assigned. write "0" when writing to this bit. if read, the value is "0". 0 : lsb first 1 : msb first uform transfer format select bit (note 3) 0 : lsb first 1 : msb first note 3: only clock synchronous serial i/o mode and 8 bit uart mode are valid.
1-111 under development specifications in this manual are tentative and subject to change rev. g serial communications mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.84. serial i/o-related registers (4) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register uart2 transmit/receive control register 1 symbol address when reset u2c1 037d 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled invalid data logic select bit 0 : no reverse 1 : reverse 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit must be fixed to ? 0 ? 0 : output disabled 1 : output enabled nothing is assigned. write "0" when writing to these bits. if read, the value is "0".
1-112 under development specifications in this manual are tentative and subject to change rev. g serial communications mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.85. serial i/o-related registers (5) note: when using multiple pins to output the transfer clock, the following requirements must be met: uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = ? 0 ? . uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 rcsp uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be ? 0 ? u0irs u1irs u0rrm u1rrm 0 : cts/rts shared pin 1 : cts/rts separated 0 : cts/rts shared pin 1 : cts/rts separated separate cts/rts bit invalid invalid invalid clk/clks select bit 1 (note) valid when bit 5 = ? 1 ? 0 : clock output to clk1 1 : clock output to clks1 uart2 special mode register symbol address when reset u2smr 0377 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss i 2 c mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : i c mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxd2 0 : disabled 1 : enabled transmit start condition select bit must always be ? 0 ? 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be ? 0 ? must always be ? 0 ? must always be ? 0 ? must always be ? 0 ? must always be ? 0 ? must always be ? 0 ? note 1: nothing but "0" may be written. note 2: when not in i 2 c mode, do not set this bit by writing a "1". during normal mode, fix it to "0". when this (note 1) sdds sda digital delay select bit (note 2, 3) 0 : analog delay output is selected 1 : digital delay output is selected (must always be "0" when not using i 2 c mode) must always be "0" bit - "0" , uart2 special mode register 3 (u2smr3 at address 037516) bits 7 to 5 (dl2 to dl0 = sda digital delay setup bits) are initialized to "000", with the analog delay circuit selected. also, when sdds = "0", do not read or write to u2smr3 register. note 3: when analog delay is selected, only the analog delay value is effective; when digital delay is selected only the digital delay value is effective. 2 nothing is assigned. write "0" when writing to this bit. if read, the value is indeterminate.
1-113 under development specifications in this manual are tentative and subject to change rev. g serial communications mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.86. serial i/o-related registers (6) symbol address when reset u2smr3 0375 16 00 16 uart2 special mode register 3 (i 2 c and spi bus exclusive use register) dl0 dl1 dl2 0 : normal mode 1 : spi mode bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 spim cpha spi mode select bit 0 0 0 : analog delay is selected 0 0 1 : 2 cycle of 1/f(x in ) 0 1 0 : 3 cycle of 1/f(x in ) 0 1 1 : 4 cycle of 1/f(x in ) 1 0 0 : 5 cycle of 1/f(x in ) 1 0 1 : 6 cycle of 1/f(x in ) 1 1 0 : 7 cycle of 1/f(x in ) 1 1 1 : 8 cycle of 1/f(x in ) b7 b6 b5 w r spi clock-phase select bit function during clock synchronous serial i/o mode function during uart mode 0 : data latched on falling clock edge 1 : data latched on rising clock edge must always be "0' must always be "0' digital delay is selected sda digital delay set up bit (notes 1, 2, 3, 4, 5) nothing is assigned. write "0" when writing to these bits. if read, the value is indeterminate. however, when sdds = "1", a "0" value is read. _ _ uart2 special mode register 2 symbol address when reset u2smr2 0376 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function stac swc2 sdhi i c mode selection bit 2 scl wait output bit 0 : disabled 1 : enabled sda output stop bit uart2 initialization bit clock-synchronous bit refer to table 1.44 0 : disabled 1 : enabled iicm2 csc swc asl 0 : disabled 1 : enabled sda output disable bit scl wait output bit 2 0: enabled 1: disabled (high impedance) 0 : disabled 1 : enabled 0: uart2 clock 1: 0 output 2 shtc start/stop condition control bit set this bit to "1" in i 2 c mode note 1: this bit can be read or written to when uart2 special mode register u2smr at address 0377 16 bit 7 (sdds: sda digital delay select bit) = "1". when the initial value of uart2 special mode register 3 (u2smr3 is read after setting sdds = "1", the value is "00 16 ". when writing to u2smr3 after setting sdds = "1", be sure to write 0s to bits 0 - 4. when sdds = "0", this register cannot be written to; when read, the value is indeterminate. note 2: these bits are initialized to "000" when sdds = "0", with the analog delay circuit selected. after a reset these bits are set to "000", with the analog delay circuit selected. however, because these bits can be read only when sdds = "1", the value read from these bits when sdds = "0" is indeterminate. note 3: when analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. note 4: the amount of delay varies with the load on scl and sda pins. also, when using an external clock, the amount of delay increases by about 100ns. be sure to take this into account when using this device. note 5: reset values for spim and cpha are not affected by the state of sdds. their reset values are always "0". (note 1)
1-114 under development specifications in this manual are tentative and subject to change rev. g clock synchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. tables 1.34 and 1.35 list the specifications of the clock synchronous serial i/o mode. figure 1.87 shows the uarti transmit/receive mode register. table 1.34. specifications of clock synchrounous serial i/o mode (1) note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: if an overrun error occurs, the uarti receive buffer will have the next data written in. also, the uart receive interrupt requst bit is not set to 1 . item specification transfer data format transfer data length: 8 bits transfer clock when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 0 ): fi/ 2 (n+1) (note 1) fi = f1, f8, f32 when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 0378 16 = 1 ): input from clki pin transmission/ reception control cts function/rts function/cts , rts function chosen to be invalid transmission start condition to start transmission, the following requirements must be met: -transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 -transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 -when cts function selected, cts input level = l if external clock is selected, the following requirements must also me be: -clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ,) = 0 : clki input level = h -clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1 : clki input level = l receiving start condition to start reception, the following requirement must be met: -receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 -transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 -transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 if external clock is selected, the following requirements must also be met: -clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0 : clki input level = h -clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1 : clki input level = l interrupt request generation timing when transmitting: -transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 0 : interrupts requested when data transferred from uarti transfer buffer register to uarti transmit register is complete -transmit interrupt cause select bit (bit 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 1 : interrupts requested when data transmission from uarti transfer reg- ister is complete when receiving: -interrupts requested when data transferred from uarti receive register to uarti receive buffer register is complete. error detection overrun error (note 2) this error occurs when the next data are ready before contents of uarti receive buffer register are read out
1-115 under development specifications in this manual are tentative and subject to change rev. g clock synchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.35. specifications of clock synchronous serial i/o mode (2) fig. 1.87. uarti transmit/receive mode register in clock synchronous serial i/o mode item specification select function clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register transfer clock output from multiple pins selection (uart1) (note) uart1 transfer clock can be chosen by software to be output from one of the two pins set switching serial data logic (uart2) whether to invert data in writing to the transmission buffer register or reading the reception buffer register can be selected. txd, rxd i/o polarity reverse (uart2) this function is inverting txd port output and rxd port input. all i/o data level are inverted, including start and stop bits. note: the transfer clock output from multple pins and the separate cts/rts pins functions cannot be selected simultaneously. separate cts/rts pins (uart0) (note) uart0 cts and rts pins each can be assigned to separate pins symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode registers internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock (note) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be ? 0 ? in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit/receive mode register internal/external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock (note 1) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode txd, rxd i/o polarity reverse bit (note) 0 : no reverse (note 2) 1 : reverse note: set the corresponding port direction register to "0". note 1: set the corresponding port direction register to "0". note 2: usually set to "0".
1-116 under development specifications in this manual are tentative and subject to change rev. g clock synchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.36 lists the functions of the input/output pins during clock synchronous serial i/o mode. this table shows the pin functions when the transfer clock output from multiple pins and the separate cts/rts pins functions are not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a ?h?. (if the n-channel open-drain is selected, this pin is in floating state). fig. 1.88 shows a typical transmit/receive timings in clock synchronous serial i/o mode. pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input transfer clock output transfer clock input programmable i/o port (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ? 0 ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ? 1 ? port p6 1 , p6 5 and p7 2 direction register (bits 1 and 5 at address 03ee 16 , bit 2 at address 03ef 16 ) = ? 0 ? port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= ? 0 ? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? 0 ? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? 0 ? port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = ? 0 ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16) = ? 0 ? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? 1 ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? 1 ? cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) table 1.36. input/output pin functions
1-117 under development specifications in this manual are tentative and subject to change rev. g clock synchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.88. typical transmit/receive timings in clock synchronous serial i/o mode stopped pulsing because transfer enable bit = ? 0 ? 1 / f ext dummy data is set in uarti transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) rtsi ? h ? ? l ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? receive enable bit (re) ? 0 ? ? 1 ? receive data is taken in transferred from uarti transmit buffer register to uarti transmit register read out from uarti receive buffer register the above timing applies to the following settings: external clock is selected. rts function is selected. clk polarity select bit = ? 0 ? . f ext : frequency of external clock transferred from uarti receive register to uarti receive buffer register receive interrupt request bit (ir) ? 0 ? ? 1 ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. meet the following conditions are met when the clk input before data reception = ? h ? transmit enable bit ? 1 ? receive enable bit ? 1 ? dummy data write to uarti transmit buffer register cleared to ? 0 ? when interrupt request is accepted, or cleared by software d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk data is set in uarti transmit buffer register tc = tclk = 2(n + 1) / fi fi: frequency of brgi count source (f 1 , f 8 , f 32 ) n: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) ? h ? ? l ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? ctsi the above timing applies to the following settings: internal clock is selected. cts function is selected. clk polarity select bit = ? 0 ? . transmit interrupt cause select bit = ? 0 ? . transmit interrupt request bit (ir) ? 0 ? ? 1 ? stopped pulsing because cts = ? h ? transferred from uarti transmit buffer register to uarti transmit register shown in ( ) are bit symbols. cleared to ? 0 ? when interrupt request is accepted, or cleared by software example of transit timing (when internal clock is selected) example of receive timing (when external clock is selected)
1-118 under development specifications in this manual are tentative and subject to change rev. g clock synchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (a) polarity select function as shown in figure 1.89, the clk polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) allows selection of the polarity of the transfer clock. (b) lsb first/msb first select function as shown in figure 1.90, when the transfer format select bit (bit 7 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = ?0?, the transfer format is ?lsb first?; when the bit = ?1?, the transfer format is ?msb first?. fig. 1.90. transfer format fig. 1.89. polarity of transfer clock when clk polarity select bit = ? 1 ? note 2: the clk pin level when not transferring data is ? l ? . d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i when clk polarity select bit = ? 0 ? note 1: the clk pin level when not transferring data is ? h ? . d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i lsb first when transfer format select bit = ? 0 ? d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i when transfer format select bit = ? 1 ? d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = ? 0 ? .
1-119 under development specifications in this manual are tentative and subject to change rev. g clock synchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (c) transfer clock output from multiple pins function (uart1) this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (see figure 1.91). the multiple pins function is valid only when the internal clock is selected for uart1. note that when this function is selected, uart1 cts/rts function cannot be used. fig. 1.91. the transfer clock output from the multiple pins function usage microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note: this applies when the internal clock is selected and transmission 1 is performed only in clock synchronous serial i/o mode. d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) txd 2 (reverse) ? h ? ? l ? ? h ? ? l ? ? h ? ? l ? when lsb first (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 03b0 16 , bit 5 at address 037d 16) is set to "1", the unit is placed in continuous receive mode. when the receive buffer register is read, the unit goes to a receive enable state without having to reset dummy data to the transmit buffer. (e) separate cts/rts pins function (uart0) refer to the clock asynchronous serial i/o mode section (page 1-124) for setting the i/o pin functions. this function is invalid if the transfer clock output from the multiple pin function is selected. (f) serial data logic switch function (uart2) when the data logic select bit (bit 6 at address 037d 16 ) = "1", the data are reversed when writing to the transmit buffer register or reading from the receive buffer register. figure 1.92 shows an example of the serial data logic switch timing function. fig. 1.92. serial data logic switch timing
1-120 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (2) clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 1.37 and 1.38 list the specifications of the uart mode. figure 1.93 shows the uarti transmit/receive mode register. table 1.37. specifications of uart mode (1) item specification transfer data format character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected start bit: 1 bit parity bit: odd, even, or none as selected stop bit: 1 bit or 2 bits as selected transfer clock when internal clock is selected (bit 3 at addresses 03a0 16 ,03a8 16 , 0378 16 = ? 0 ? ): fi/16(n+1) (note 1) fi = f 1 , f 8 , f 32 when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 = ? 1 ? ): f ext /16(n+1) (note 1) (note 2) cts function/rts function/cts, rts function chosen to be invalid to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = ? 1 ? - tr ansmit buffer empty flag (bit 1 at addresses 03a5 16 ,03ad 16 ,037d 16 )= ? 0 ? - when cts function selected, cts input level = ? l ? receive start condition to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = ? 1 ? - start bit detection interrupt request when transmitting generation timing - t ransmit interrupt cause select bits (bits 0,1 at address 03b0 16 , bit4 at address 037d 16 ) = ? 0 ? : interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 03b0 16 , bit4 at address 037d 16 ) = ? 1 ? : interrupts requested when data transmission from uarti transfer register is completed when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection overrun error (note 3) this error occurs when the next character is received before contents of uarti receive buffer register are read out framing error this error occurs when the number of stop bits set is not detected parity error this error occurs when if parity is enabled, the number of 1 ? s in parity and character bits does not match the number of 1 ? s set error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered note 1: ? n ? denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will have the last or most recent data written to it. note also that uarti receive interrupt requst bit is not set to "1" transmit/receive control transmit start condition
1-121 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.93. uarti transmit/receive mode register in uart mode table 1.38. specifications of uart mode (2) item specification select function separate cts/rts pins (uart0) uart0 cts and rts functions each can be assigned to separate pins sleep mode selection (uart0, uart1) this mode is used to transfer data to and from one of multiple slave micro- computers serial data logic switch (uart2) this function inverts logic value of transferring data. start bit, parity bit and stop bit are not inverted. t x d, r x d i/o polarity switch this function inverts t x d port output and r x d port input. all i/o data level is are inverted. symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit / receive mode registers internal / external clock select bit stps pry prye slep 0 : internal clock 1 : external clock (note) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 1 ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit sleep select bit symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit / receive mode register internal / external clock select bit stps pry prye iopol must always be fixed to ? 0 ? bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 1 ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit txd, rxd i/o polarity reverse bit (note) note: usually set to ? 0 ? . note: set the corresponding port direction register to "0".
1-122 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.39lists the functions of the input/output pins during uart mode. this table shows the pin functions when the separate cts/rts pins function is not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a ?h?. (if the n-channel open-drain is selected, this pin is in floating state). figures 1.94 and 1.95 show the typical transmit timings in uart mode (uart0, uart1, uart2). figure 1.96 shows the typical receive timing in uart mode. table 1.39. input/output pin functions in uart mode pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input programmable i/o port transfer clock input programmable i/o port rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ? 0 ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ? 1 ? port p6 1 , p6 5 direction register (bits 1 and 5 at address 03ee 16 ) = ? 0 ? port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= ? 0 ? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? 0 ? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? 0 ? port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = ? 0 ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16) = ? 0 ? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? 1 ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? 1 ? cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) (when separate cts/rts pins function is not selected)
1-123 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.94. typical transmit timings in uart mode (uart0, uart1) transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) ? 0 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? the above timing applies to the following settings : parity is disabled. two stop bits. cts function is disabled. transfer clock tc tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? 0 ? ? 1 ? shown in ( ) are bit symbols. start bit data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit sp cleared to ? 0 ? when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi ctsi the above timing applies to the following settings : parity is enabled. one stop bit. cts function is selected. transmit interrupt cause select bit = ? 1 ? . ? 1 ? ? 0 ? ? 1 ? ? l ? ? h ? ? 0 ? ? 1 ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? 0 ? ? 1 ? cleared to ? 0 ? when interrupt request is accepted, or cleared by software shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st psp d 0 d 1 st stopped pulsing because transmit enable bit = ? 0 ? stop bit transferred from uarti transmit buffer register to uarti transmit register the transfer clock stops momentarily as cts is ? h ? when the stop bit is checked. the transfer clock starts as the transfer starts immediately cts changes to ? l ? . data is set in uarti transmit buffer register. ? 0 ? example of transmit timing when transfer data is 8 bits long (parity enabled, one-stop bit) example of transmit timing when tranfer data is 9 bits long (parity disabled, two-stop bits) transmit interrupt cause select bit = "0".
1-124 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.95. typical transmit timings in uart mode (uart2) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit cleared to ? 0 ? when interrupt request is accepted, or cleared by software d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p tc sp stop bit data is set in uart2 transmit buffer register transferred from uart2 transmit buffer register to uarti transmit register sp transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) ? 0 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? transmit interrupt request bit (ir) ? 0 ? ? 1 ? transfer clock txd 2 the above timing applies to the following settings : parity is enabled. one stop bit. transmit interrupt cause select bit = ? 1 ? . tc = 16 (n + 1) / fi fi : frequency of brg2 count source (f 1 , f 8 , f 32 ) n : value set to brg2 shown in ( ) are bit symbols. note note: the transmit is started with overflow timing of brg after having written in a value at the transmit buffer in the above t iming. example of transmit timing when tranfer data is 8 bits long (parity enabled, one-stop bit) d 0 start bit sampled ? l ? receive data taken in brgi count source receive enable bit rxdi transfer clock receive complete flag rtsi stop bit ? 1 ? ? 0 ? ? 0 ? ? 1 ? ? h ? ? l ? the above timing applies to the following settings : parity is disabled. one stop bit. rts function is selected. receive interrupt request bit ? 0 ? ? 1 ? transferred from uarti receive register to uarti receive buffer register reception triggered when transfer clock is generated by falling edge of start bit d 7 d 1 cleared to ? 0 ? when interrupt request is accepted, or cleared by software example of receive timing when tranfer data is 8 bits long (parity disabled, one-stop bit) ....... ....... ....... fig. 1.96. typical receive timing in uart mode
1-125 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (b) sleep mode (uart0, uart1) this mode is used to transfer data between specific microcomputers among multiple microcomputers connected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 03a0 16 , 03a8 16 ) is set to ?1? during reception. in this mode, the unit performs receive operation when the msb of the received data = ?1? and does not perform receive operation when the msb = ?0?. (c) function for switching serial data logic (uart2) when the data logic select bit (bit 6 of address 037d 16 ) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. figure 1.98 shows the example of timing for switching serial data logic. fig. 1.97. the separate cts/rts pins function usage fig. 1.98. timing for switching serial data logic microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts0 (p6 4 ) rts0 (p6 0 ) ic note : the user cannot use cts and rts at the same time. st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd 2 (no reverse) txd 2 (reverse) ? h ? ? l ? ? h ? ? l ? ? h ? ? l ? example of timing for switching serial data logic when lsb is first (parity enabled, one-stop bit) (a) separate cts/rts pins function (uart0) setting the cts/rts separate bit (bit 6 of address 03b0 16 ) to "1" inputs/outputs the cts signal and rts signal from different pins. choose which to use, cts or rts, by use of the cts/rts function select bit (bit 2 of address 03a4 16 ). (see fig. 1.97). this function is effective in uart0 only. with this function chosen, the user cannot use the cts/rts function. set "0" both to the cts/rts function select bit (bit 2 of address 03ac 16 ) and to the cts/rts disable bit (bit 4 of address 03ac 16 ).
1-126 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (d) txd, rxd i/o polarity reverse function (uart2) this function is to reverse t x d pin output and r x d pin input. the level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. set this function to ?0? (not to reverse) for normal use. (e) bus collision detection function (uart2) this function is to sample the output level of the t x d pin and the input level of the r x d pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. figure 1.99 shows the example of detection timing of a bus collision (in uart mode). fig. 1.99. detection timing of a bus collision (in uart mode) st : start bit sp : stop bit st st sp sp transfer clock txd 2 rxd 2 bus collision detection interrupt request signal ? h ? ? l ? ? h ? ? l ? ? h ? ? l ? ? 1 ? ? 0 ? bus collision detection interrupt request bit ? 1 ? ? 0 ?
1-127 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (3) clock-asynchronous serial i/o mode (compliant with the sim interface) the sim interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in uart2 clock-asynchronous serial i/o mode allows the user to effect this function. table 1.40 shows the specifications of clock-asynchronous serial i/o mode (compliant with the sim interface). figure 1.100 shows a typical transmit/receive timing in uart mode (compliant with the sim interface). item specification transfer data format transfer data 8-bit uart mode (bit 2 through bit 0 of address 0378 16 = ? 101 2 ? ) one stop bit (bit 4 of address 0378 16 = ? 0 ? ) with the direct format chosen set parity to ? even ? (bit 5 and bit 6 of address 0378 16 = ? 1 ? and ? 1 ? respect ively) set data logic to ? direct ? (bit 6 of address 037d 16 = ? 0 ? ). set transfer format to lsb (bit 7 of address 037c 16 = ? 0 ? ). with the inverse format chosen set parity to ? odd ? (bit 5 and bit 6 of address 0378 16 = ? 0 ? and ? 1 ? respectively) set data logic to ? inverse ? (bit 6 of address 037d 16 = ? 1 ? ) set transfer format to msb (bit 7 of address 037c 16 = ? 1 ? ) transfer clock wi th the i nt er nal cl ock chosen ( bi t 3 of addr ess 0378 16 = ? 0 ? ) : fi /16(n+1) (note1) :fi=f 1 ,f 8 ,f 32 (do not use external clock) transmit/receive control disable the cts and rts function (bit 4 of address 037c 16 = ? 1 ? ) other settings the sleep mode select function is not available for uart2 set transmission interrupt factor to ? transmissioncompleted ? ( bi t 4 of addr ess 037d 16 = ? 1 ? ) tr ansmit start condition to start transmission, the following requirements must be met: - transmit enable bit (bit 0 of address 037d 16 ) = ? 1 ? - transmit buffer empty flag (bit 1 of address 037d 16 ) = ? 0 ? receive start condition to start reception, the following requirements must be met: - reception enable bit (bit 2 of address 037d 16 ) = ? 1 ? - detection of a start bit when transmitting when data transmission from the uart2 transfer register is completed (bit 4 of address 037d 16 = ? 1 ? ) when receiving when data transfer from the uart2 receive register to the uart2 receive buffer register is completed error detection overrun error (see the specifications of clock-asynchronous serial i/o) (note 2) framing error (see the specifications of clock-asynchronous serial i/o) parity error (see the specifications of clock-asynchronous serial i/o) - on the reception side, an ? l ? level is output from the t x d 2 pin by use of the parity error signal output function (bit 7 of address 037d 16 = ? 1 ? ) when a parity error is detected - on the transmission side, a parity error is detected by the level of input to the r x d 2 pin when a transmission interrupt occurs the error sum flag (see the specifications of clock-asynchronous serial i/o) interrupt request generation timing note 1: ? n ? denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: if an overrun error occurs, the uart2 receive buffer will have the last or most recent data written. note also the uarti receive interrupt request bit is not set to "1". table 1.40. specifications of clock-asynchronous serial i/o mode (compliant with the sim interface)
1-128 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.100. typical transmit/receive timing in uart mode (compliant with the sim interface) transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit the above timing applies to the following settings : parity is enabled. one stop bit. transmit interrupt cause select bit = ? 1 ? . ? 0 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? tc = 16 (n + 1) / fi fi : frequency of brg2 count source (f 1 , f 8 , f 32 ) n : value set to brg2 transmit interrupt request bit (ir) ? 0 ? ? 1 ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p shown in ( ) are bit symbols. tc transfer clock sp stop bit data is set in uart2 transmit buffer register sp a ? l ? level returns from txd 2 due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine. receive enable bit (re) receive complete flag (ri) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit rxd 2 the above timing applies to the following settings : parity is enabled. one stop bit. transmit interrupt cause select bit = ? 0 ? . ? 0 ? ? 1 ? ? 0 ? ? 1 ? tc = 16 (n + 1) / fi fi : frequency of brg2 count source (f 1 , f 8 , f 32 ) n : value set to brg2 receive interrupt request bit (ir) ? 0 ? ? 1 ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp shown in ( ) are bit symbols. tc transfer clock sp stop bit a ? l ? level returns from txd 2 due to the occurrence of a parity error. txd 2 read to receive buffer read to receive buffer d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p signal conductor level (note 1) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 signal conductor level (note 1) note: equal in waveform because txd 2 and rxd 2 are connected. transferred from uart2 transmit buffer register to uart2 transmit register cleared to ? 0 ? when interrupt request is accepted, or cleared by software cleared to ? 0 ? when interrupt request is accepted, or cleared by software note: the transmit is started with overflow timing of brg after having written in a value at the transmit buffer in the above t iming. note
1-129 under development specifications in this manual are tentative and subject to change rev. g clock asynchronous serial i/o mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (b) direct format/inverse format connecting the sim card allows you to switch between direct format and inverse format. if you choose the direct format, d0 data is output from txd2. if you choose the inverse format, d7 data is inverted and output from txd2. figure 1.102 shows the sim interface format. figure 1.103 shows the example of connecting the sim interface. connect t x d 2 and r x d 2 and apply pull-up. fig. 1.101. output timing of the parity error signal fig. 1.102. sim interface format fig. 1.103. connecting the sim interface (a) function for outputting a parity error signal with the error signal output enable bit (bit 7 of address 037d 16 ) assigned ?1?, you can output an ?l? level from the txd2 pin when a parity error is detected. in step with this function, the generation timing of a trans- mission completion interrupt changes to the detection timing of a parity error signal. figure 1.101 shows the output timing of the parity error signal. st : start bit p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p sp st hi-z transfer clock rxd 2 txd 2 receive complete flag ? h ? ? l ? ? h ? ? l ? ? h ? ? l ? ? 1 ? lsb first ? 0 ? sp: stop bit p : even parity st: start bit sp: stop bit d0 d1 d2 d3 d4 d5 d6 d7 p transfer clock txd 2 (direct) txd 2 (inverse) d7 d6 d5 d4 d3 d2 d1 d0 p st st sp sp microcomputer sim card txd 2 rxd 2
1-130 under development specifications in this manual are tentative and subject to change rev. g uart2 in i 2 c mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer uart2 in i 2 c mode the uart2 special mode register (address 0377 16 ) is used to control uart2 in various ways. figure 1.104 shows the uart2 special mode register. setting the i 2 c mode select bit (bit 1 of u2smr) to "1" selects i 2 c mode. table 1.41 shows the relation between the i 2 c mode select bit and respective control workings. since this function uses clock-synchronous serial i/o mode, set this bit to ?0? in uart mode. table 1.41. features in i 2 c mode function normal mode i 2 c mode (note 1) source for interrupt number 15 (note 2) uart2 transmission no acknowledgment detection (nack) source for interrupt number 16 (note 2) uart2 reception start condition detection or stop condition detection uart2 transmission output delay not delayed delayed p7 0 at the time when uart2 is in use txd 2 (output) sda (input/output) (note 3) p7 1 at the time when uart2 is in use rxd 2 (input) scl (input/output) p7 2 at the time when uart2 is in use clk 2 p7 2 dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits uart2 reception acknowledgment detection (ack) noise filter width 15ns 50ns reading p7 1 reading the terminal when 0 is assigned to the direction register reading the terminal regardless of the value of the direction register 1 2 3 4 5 6 7 8 9 note 1: make the settings given below when i 2 c mode is in use. set 0 1 0 in bits 2, 1, 0 of the uart2 transmission/reception mode register. disable the rts/cts function. choose the msb first function. note 2: follow the steps given below to switch from a factor to another. 1. disable the interrupt of the corresponding number. 2. switch from one source to another. 3. reset the interrupt request flag of the corresponding number. 4. set an interrupt level of the corresponding number. note 3: set an initial value of sda transmission output when serial i/o is invalid. source for interrupt number 10 (note 2) bus collision detection acknowledgment detection (ack) 10 initial value of uart2 output h level (when 0 is assigned to the clk polarity select bit) the value set in latch p7 0 when the port is selected 11
1-131 under development specifications in this manual are tentative and subject to change rev. g uart2 in i 2 c mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.104. uart2 special mode register symbol address when reset u2smr3 0375 16 00 16 uart2 special mode register 3 (i 2 c and spi bus exclusive use register) dl0 dl1 dl2 0 : normal mode 1 : spi mode bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 spim cpha spi mode select bit 0 0 0 : analog delay is selected 0 0 1 : 2 cycle of 1/f(x in ) 0 1 0 : 3 cycle of 1/f(x in ) 0 1 1 : 4 cycle of 1/f(x in ) 1 0 0 : 5 cycle of 1/f(x in ) 1 0 1 : 6 cycle of 1/f(x in ) 1 1 0 : 7 cycle of 1/f(x in ) 1 1 1 : 8 cycle of 1/f(x in ) b7 b6 b5 w r spi clock-phase select bit function during clock synchronous serial i/o mode function during uart mode 0 : data latched on falling clock edge 1 : data latched on rising clock edge must always be "0' must always be "0' digital delay is selected sda digital delay set up bit (note 1, 2, 3, 4, 5) nothing is assigned. in an attempt to write to these bits, write "0". when read the value is indeterminate. however, when sdds = "1", a "0" value is read. _ _ note 1: this bit can be read or written to when uart2 special mode register u2smr at address 0377 16 bit 7 (sdds: sda digital delay select bit) = "1". when the initial value of uart2 special mode register 3 (u2smr3 is read after setting sdds = "1", the value is "00 16 ". when writing to u2smr3 after setting sdds = "1", be sure to write 0s to bits 0 - 4. when sdds = "0", this register cannot be written to; when read, the value is indeterminate. note 2: these bits are initialized to "000" when sdds = "0", with the analog delay circuit selected. after a reset these bits are set to "000", with the analog delay circuit selected. however, because these bits can be read only when sdds = "1", the value read from these bits when sdds = "0" is indeterminate. note 3: when analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. note 4: the amount of delay varies with the load on scl and sda pins. also, when using an external clock, the amount of delay increases by about 100ns. be sure to take this into account when using this device. note 5: reset values for spim and cpha are not affected by the state of sdds. their reset values are always "0". (note 1) uart2 special mode register symbol address when reset u2smr 0377 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss iic mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : iic mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxd2 0 : disabled 1 : enabled transmit start condition select bit must always be ? 0 ? 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be ? 0 ? must always be ? 0 ? must always be ? 0 ? must always be ? 0 ? must always be ? 0 ? must always be ? 0 ? note 1: nothing but "0" may be written. note 2: when not in i 2 c mode, do not set this bit by writing a "1". during normal mode, fix it to "0". when this (note 1) sdds sda digital delay select bit (note 2, 3) 0 : analog delay output is selected 1 : digital delay output is selected (must always be "0" when not using i 2 c mode) must always be "0" bit - "0" , uart2 special mode register 3 (u2smr3 at address 037516) bits 7 to 5 (dl2 to dl0 = sda digital delay setup bits) are initialized to "000", with the analog delay circuit selected. also, when sdds = "0", the u2smr3 register cannot be read or written to. note 3: when analog delay is selected, only the analog delay value is effective; when digital delay is selected only the digital delay value is effective.
1-132 under development specifications in this manual are tentative and subject to change rev. g uart2 in i 2 c mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.105 shows the functional block diagram for i 2 c mode. setting ?1? in the i 2 c mode select bit (iicm) causes ports p7 0 , p7 1 , and p7 2 to work as data transmission-reception terminal sda, clock input-output terminal scl, and port p7 2 respectively. a delay circuit is added to the sda transmission output, so the sda output changes after scl fully goes to ?l?. the sda digital delay select bit (bit 7 at address 0377 16 ) can be used to select between analog delay and digital delay. when digital delay is selected, the amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using uart2 special mode register 3 (at address 0375 16 ). delay circuit select conditions are shown in table 1.42. table 1.42. delay circuit select conditions fig. 1.105. functional block diagram for i 2 c mode p7 0 through p7 2 conforming to the simplified i c bus selector i/o timer delay noise filter timer uart2 selector (port p7 1 output data latch) i/o p7 0 /txd 2 /sda p7 1 /rxd 2 /scl reception register clk internal clock uart2 external clock selector uart2 i/o timer p7 2 /clk 2 arbitration start condition detection stop condition detection data bus falling edge detection d t q d t q d t q nack ack uart2 uart2 uart2 r uart2 transmission/ nack interrupt request uart2 reception/ack interrupt request dma1 request 9th pulse iicm=1 iicm=0 iicm=1 iicm=0 iicm=1 iicm=0 iicm=0 iicm=1 iicm=0 iicm=1 iicm=1 iicm=0 port reading * with iicm set to 1, the port terminal is to be readable even if 1 is assigned to p7 1 of the direction register. l-synchronous output enabling bit s r q bus busy iicm=1 iicm=0 bus collision/start, stop condition detection interrupt request bus collision detection noise filter transmission register to dma0, dma1 q noise filter to dma0 2 sdds = "0" or dl = "000" digital delay is selected analog delay is selected no delay 1 1 0 1 1 0 0 001 to 111 000 (000) (000) when digital delay is selected,no analog delay is added. only digital delay is effective when dl is set ot "000", analog delay is selected no matter what value is set in sdds. when sdds is set to "0", dl is initialized, so that dl = "000". when iicm = "0", no delay circuit is selected. always made sure sdds = "0". register value iicm sdds dl contents
1-133 under development specifications in this manual are tentative and subject to change rev. g uart2 in i 2 c mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer an attempt to read port p7 1 (scl) gets the pin's level regardless of the content of the port direction register. the initial value of sda transmission output in this mode goes to the value set in port p7 0 . the interrupt factors of the bus collision detection interrupt, uart2 transmission interrupt, and of uart2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. the start condition detection interrupt refers to the interrupt that occurs when the falling edge of the sda terminal (p7 0 ) is detected with the scl terminal (p7 1 ) staying ?h?. the stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the sda terminal (p7 0 ) is detected with the scl terminal (p7 1 ) staying ?h?. the bus busy flag (bit 2 of the uart2 special mode register) is set to ?1? by the start condition detection, and set to ?0? by the stop condition detection. the acknowledgment non-detection interrupt refers to the interrupt that occurs when the sda terminal level is detected still staying ?h? at the rising edge of the 9th transmission clock. the acknowledgment detection interrupt refers to the interrupt that occurs when sda terminal?s level is detected already went to ?l? at the 9th transmission clock. also, assigning 1 1 0 1 (uart2 reception) to the dma1 request factor select bits provides the means to start up the dma transfer by the effect of acknowledgment detection. bit 1 of the uart2 special mode register (0377 16 ) is used as the arbitration loss detecting flag control bit. arbitration means the act of detecting the nonconformity between transmission data and sda termi- nal data at the timing of the scl rising edge. this detecting flag is located at bit 3 of the uart2 reception buffer register (037f 16 ), and ?1? is set in this flag when nonconformity is detected. use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. when setting this bit to ?1? and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to ?1? at the falling edge of the 9th transmission clock. if update the flag byte by byte, must judge and clear (?0?) the arbitration lost detecting flag after complet- ing the first byte acknowledge detect and before starting the next one byte transmission. bit 3 of the uart2 special mode register is used as scl- and l-synchronous output enable bit. setting this bit to ?1? goes the p7 1 data register to ?0? in synchronization with the scl terminal level going to ?l?. some other functions added are explained here. figure 1.106 shows their workings. bit 4 of the uart2 special mode register is used as the bus collision detect sampling clock select bit. the bus collision detect interrupt occurs when the rxd2 level and txd2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to ?0?. if this bit is set to ?1?, the nonconformity is detected at the timing of the overflow of timer a0 rather than at the rising edge of the transfer clock.
1-134 under development specifications in this manual are tentative and subject to change rev. g uart2 in i 2 c mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.106. some other functions added bit 5 of the uart2 special mode register is used as the auto clear function select bit of transmit enable bit. setting this bit to ?1? automatically resets the transmit enable bit to ?0? when ?1? is set in the bus collision detect interrupt request bit (nonconformity). bit 6 of the uart2 special mode register is used as the transmit start condition select bit. setting this bit to ?1? starts the txd transmission in synchronization with the falling edge of the rxd terminal. 1. bus collision detect sampling clock select bit (bit 4 of the uart2 special mode register) 0: rising edges of the transfer clock clk timer a0 1: timer a0 overflow 2. auto clear function select bit of transmt enable bit (bit 5 of the uart2 special mode register) clk txd/rxd bus collision detect interrupt request bit transmit enable bit 3. transmit start condition select bit (bit 6 of the uart2 special mo de register) clk txd enabling transmission clk txd rxd with "1: falling edge of rxd 2 " selected 0: in normal state txd/rxd
1-135 under development specifications in this manual are tentative and subject to change rev. g uart2 in i 2 c mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.43. functions changed by i 2 c mode select bit 2 uart2 special mode register 2 uart2 special mode register 2 (address 0376 16 ) is used to further control uart2 in i 2 c mode. figure 1.107 shows the uart2 special mode register 2. bit 0 of the uart2 special mode register 2 (address 0376 16 ) is used as the i 2 c mode select bit 2. table 1.43 shows the types of control to be changed by i 2 c mode select bit 2 when the i 2 c mode select bit is set to ?1?. figure 1.108 shows the timing characteristics of detecting the start condition and the stop condition. set the start/stop condition control bit (bit 7 of uart2 special mode register 2) to ?1? in i 2 c mode. fig. 1.107. uart2 special mode register 2 function iicm2 = 1 iicm2 = 0 factor of interrupt number 15 no acknowledgment detection (nack) uart2 transmission (the rising edge of the final bit of the clock) factor of interrupt number 16 acknowledgment detection (ack) uart2 reception (the falling edge of the final bit of the clock) dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits acknowledgment detection (ack) uart2 reception (the falling edge of the final bit of the clock) timing for transferring data from the uart2 reception shift register to the reception buffer. the rising edge of the final bit of the reception clock the falling edge of the final bit of the reception clock timing for generating a uart2 reception/ack interrupt request the rising edge of the final bit of the reception clock the falling edge of the final bit of the reception clock 1 2 3 4 5 uart2 special mode register 2 symbol address when reset u2smr2 0376 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function stac swc2 sdhi i c mode selection bit 2 scl wait output bit 0 : disabled 1 : enabled sda output stop bit uart2 initialization bit clock-synchronous bit refer to table 1.43 0 : disabled 1 : enabled iicm2 csc swc asl 0 : disabled 1 : enabled sda output disable bit scl wait output bit 2 0: enabled 1: disabled (high impedance) 0 : disabled 1 : enabled 0: uart2 clock 1: 0 output (note) 2 shtc start/stop condition control bit set this bit to "1" in i 2 c mode (refer to figure 1.108)
1-136 under development specifications in this manual are tentative and subject to change rev. g uart2 in i 2 c mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer bit 3 of the uart2 special mode register 2 (address 0376 16 ) is used as the sda output stop bit. setting this bit to ?1? causes an arbitration loss to occur, and the sda pin turns to high-impedance state the instant when the arbitration loss detection flag is set to ?1?. bit 1 of the uart2 special mode register 2 (address 0376 16 ) is used as the clock synchronization bit. with this bit set to ?1? at the time when the internal scl is set to ?h?, the internal scl turns to ?l? if the falling edge is found in the scl pin; and the baud rate generator reloads the set value, and start counting within the ?l? interval. when the internal scl changes from ?l? to ?h? with the scl pin set to ?l?, stops counting the baud rate generator, and starts counting it again when the scl pin turns to ?h?. due to this function, the uart2 transmission-reception clock becomes the logical product of the signal flowing through the internal scl and that flowing through the scl pin. this function operates over the period from the moment earlier by a half cycle than falling edge of the uart2 first clock to the rising edge of the ninth bit. to use this function, choose the internal clock for the transfer clock. bit 2 of the uart2 special mode register 2 (0376 16 ) is used as the scl wait output bit. setting this bit to ?1? causes the scl pin to be fixed to ?l? at the falling edge of the ninth bit of the clock. setting this bit to ?0? frees the output fixed to ?l?. bit 4 of the uart2 special mode register 2 (address 0376 16 ) is used as the uart2 initialization bit. setting this bit to ?1?, and when the start condition is detected, the microcomputer operates as follows. (1) the transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. this starts transmission by dealing with the clock entered next as the first bit. the uart2 output value, however, doesn?t change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) the reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) the scl wait output bit turns to ?1?. this turns the scl pin to ?l? at the falling edge of the ninth bit of the clock. fig. 1.108. timing characteristics of detecting the start condition and the stop condition (note1) 3 to 6 cycles < duration for setting-up (note 2) 3 to 6 cycles < duration for holding (note 2) note 1 : when the start/stop condition count bit is "1" . note 2 : "cycles" is in terms of the input oscillation frequency f(xin) of the main clock. duration for setting up duration for holding scl sda (start condition) sda (stop condition)
1-137 under development specifications in this manual are tentative and subject to change rev. g uart2 in i 2 c mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer starting to transmit/receive signals to/from uart2 using this function doesn?t change the value of the transmission buffer empty flag. to use this function, choose the external clock for the transfer clock. bit 5 of the uart2 special mode register 2 (0376 16 ) is used as the scl pin wait output bit 2. setting this bit to ?1? with the serial i/o specified allows the user to output an ?1? from the scl pin even if uart2 is in operation. setting this bit to ?0? frees the ?l? output from the scl pin, and the uart2 clock is input/output. bit 6 of the uart2 special mode register 2 (0376 16 ) is used as the sda output disable bit. setting this bit to ?1? forces the sda pin to turn to the high-impedance state. refrain from changing the value of this bit at the rising edge of the uart2 transfer clock. there can be instances in which arbitration lost detection flag is turned on.
1-138 under development specifications in this manual are tentative and subject to change rev. g uart2 in spi mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer uart2 in spi mode the uart2 special mode register 3 (address 0375 16 ) is used to activate the spi mode. figure 1.109 shows the uart2 special mode register 3. fig. 1.109. uart2 special mode register 3 symbol address when reset u2smr3 0375 16 00 16 uart2 special mode register 3 (i 2 c and spi bus exclusive use register) dl0 dl1 dl2 0 : normal mode 1 : spi mode bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 spim cpha spi mode select bit 0 0 0 : analog delay is selected 0 0 1 : 2 cycle of 1/f(x in ) 0 1 0 : 3 cycle of 1/f(x in ) 0 1 1 : 4 cycle of 1/f(x in ) 1 0 0 : 5 cycle of 1/f(x in ) 1 0 1 : 6 cycle of 1/f(x in ) 1 1 0 : 7 cycle of 1/f(x in ) 1 1 1 : 8 cycle of 1/f(x in ) b7 b6 b5 w r spi clock-phase select bit function during clock synchronous serial i/o mode function during uart mode 0 : data latched on falling clock edge 1 : data latched on rising clock edge must always be "0' must always be "0' digital delay is selected sda digital delay set up bit (note 1, 2, 3, 4, 5) nothing is assigned. in an attempt to write to these bits, write "0". when read the value is indeterminate. however, when sdds = "1", a "0" value is read. _ _ note 1: this bit can be read or written to when uart2 special mode register u2smr at address 0377 16 bit 7 (sdds: sda digital delay select bit) = "1". when the initial value of uart2 special mode register 3 (u2smr3 is read after setting sdds = "1", the value is "00 16 ". when writing to u2smr3 after setting sdds = "1", be sure to write 0s to bits 0 - 4. when sdds = "0", this register cannot be written to; when read, the value is indeterminate. note 2: these bits are initialized to "000" when sdds = "0", with the analog delay circuit selected. after a reset these bits are set to "000", with the analog delay circuit selected. however, because these bits can be read only when sdds = "1", the value read from these bits when sdds = "0" is indeterminate. note 3: when analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. note 4: the amount of delay varies with the load on scl and sda pins. also, when using an external clock, the amount of delay increases by about 100ns. be sure to take this into account when using this device. note 5: reset values for spim and cpha are not affected by the state of sdds. their reset values are always "0". (note 1)
1-139 under development specifications in this manual are tentative and subject to change rev. g uart2 in spi mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer the spi functionality is an 8 bit, synchronous communication protocol that is user programmable to use one of four different transfer formats. the four transfer formats support the four combinations of clock phase and clock polarity, as the clock relates to the data. figure 1.110 shows the spi system level view. the existing uart2 already provides two of the transfer formats, with the ckpol control bit. the spi mode adds the ability to change the phase of the clock, with respect to the transmitted data, in each of the two existing clock polarity formats. fig. 1.110. spi system level view when operated in spi mode the uart2 package pins provide the alternate spi functions. mosi, master out slave in, is multiplexed on pin p7[0]/txd2. mosi outputs data when uart2 is a spi master and inputs data when uart2 is a spi slave. miso, master in slave out, is multiplexed on pin p7[1]/ rxd2. miso inputs data when uart2 is a spi master and outputs data when uart2 is a spi slave. spiclk, spi clock, is multiplexed on pin p7[2]/clk2. the spi clock is input when the spi is configured as a slave or output when the spi is configured as a master. ssb, slave select input, is multiplexed on pin p7[3]/rtsb/ctsb. this pin is used to select the active spi slave. the M30222 uart2 can be operated as an spi master or as an spi slave. operation as an spi slave or spi master is determined by the ckdir contol bit. while in spi mode, the txd and rxd pins act as the spi mosi and miso pins. as implemented on the M30222, the spi pins mosi and miso are open drain. there are two added control bits and one added status flag. control bit spim is the spi mode enable, which enables spi operation. cpha is the clock phase selection control bit. cpha is used to chooses the clock to data relationship. combined with the existing ckpol control bit, cpha provides compat- ibility with all four spi transmission modes. cpha is held at ?0? when spim = ?0?. the status flag mdflt is used to indicate that an spi mode fault occurred. several existing configuration bits are required for spi operation. spi slave / master mode is controlled by the existing ckdir control bit. the uart is in spi master mode when the clock is generated internally and is in spi slave mode when the clock is generated externally. ckpol control bit select the master mcu slave mcu miso mosi spiclk ssb miso mosi spiclk ssb csb slave mcu s ssb input may be tied to ground if there is only one spi slave in the system.
1-140 under development specifications in this manual are tentative and subject to change rev. g uart2 in spi mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer polarity of the transfer clock. the four different combinations of ckpol and cpha define the four formats of the spi communication protocols. while in spi mode, the crd control bit enables the cts/ rts pin to operate as ssb and crs control bit selects cts/rts pin to operate as cts/ ssb. both contorl bits must be properly configured to activate the ssb function. uform control bit selects the uart transfer format, msb or lsb. spi data is transmitted msb first. spi operation setting smd[2:0]=010 in u2mr enables either spi or iic operation. operation is undefined if both iicm (u2smr[0]) and spi (u2smr3[0]) control bits are set to logic one while smd[2:0]=010. setting the spim control bit puts the uart2 into an spi compatible mode. this mode is only valid in the clock synchronous configuration and must not be entered when the uart2 is configured for asynchronous operation. the internal / external clock select bit (ckdir) in u2mr) determines whether uart2 is an spi master or slave. if internal clock is selected, the uart is an spi master and if external clock is selected, uart2 is an spi slave. figure 1.111 shows the signal wave forms. entering spi mode has the following effects on operation: (1) an alternate clock to data relationship can be chosen with the cpha bit (in u2smr3). this bit can only be set when spi bit is a ?1?. all four spi clock to data formats are possible by using the cpha bit together with the ckpol bit (in u2c0). figure 1.112 shows the function block diagram of spi mode. (2) the rxd pin becomes the miso pin. (3) the txd pin becomes the mosi pin. (4) p7[3]/ctsb/rtsb functions as the slave select input. this input is active low. (5) when configured as a master, a mode fault will be detected if the slave select input goes low. if no port pin is assigned to be a slave select input, then mode fault detection is disabled. fig. 1.111. spi transmission formats note: to prevent spurious clock transitions, configure the spi modules as master or slave before enabling them. enable the master before enabling the slave. disable the slave before disabling the master. ckpol = 1 cpha = 1 ckpol = 1 cpha = 0 ckpol = 0 cpha = 1 ckpol = 0 cpha = 0 ssb sclk sclk sclk sclk miso/mosi msb lsb
1-141 under development specifications in this manual are tentative and subject to change rev. g uart2 in spi mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.112 functional block diagram of spi mode selector transmit register clkdir receive register clkdir = 1 = slave = 0 = master timer i/o timer i/o selector clkdir timer i/o selector clkdir clock generator transmit receive control ss clock phase shift clock polarity invert clkdir ckpol cpha timer i/o selector mode fault detect clkdir s r q mdflt uart2 reset p7 3 /ss p7 2 /spiclk p7 1 /miso p7 0 /mosi spi mode functional block diagram
1-142 under development specifications in this manual are tentative and subject to change rev. g uart2 in spi mode mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer master mode operation spi master mode is entered by setting both spi and ckdir control bits to logic one. in master mode, the uart will generate the clock to be driven on spiclk. transmitted data is shifted out on mosi and and receive data is shifted in on miso. the mode fault status flag, mdflt, is set any time the state of the slave select pin, ss, is inconsistent with an active spi mode, spimstr or spislv. detection is intended to protect the mcu from damage due to output driver contention. a mode fault occurs if the ss pin of a slave spi goes high during a transmissionor if the ss pin of a master spi goes low at any time a mode fault causes the following: (1) the clkdir bit (in u2mr is forced to a ?1?. this puts the uart into slave mode so that it is not driving the clk and mosi pins. (2) the uart is inhibited from driving it?s miso pin. (3) mode fault, mdf, status bit (bit 10 of u2rb) is set. a uart2 receiver interrupt is generated. mode fault detection is disabled when the cts2 /ssb function is not assigned to a port pin. in this case, slave select is internally negated if the uart is configured for spi master operation. a mode fault is cleared by setting the serial i/o mode bits (bits 2 through 0 of u2mr) to ?000?. also, the receiver enable bit (re2 of u2c1) must be cleared. when the mode fault is cleared, the uart will return to master mode unless the crs bit (in u2c0) is explicitly set. slave mode operation spi slave mode is entered by setting the spi control bit to logic one and the ckdir control bit to logic zero. before transmission can start, the ssb pin of the slave spi must be at logic zero. when configured as a spi slave, uart2 does not initiate any serial transfers. all transfers are initiated by an external spi bus master. when the cpha bit is a ?1?, serial transfers begin with the falling edge of slave select. for cpha = ?0?, serial transfers begin when the clk leaves it?s idle state (the clock idle state is defined by the ckpol bit in u2c0). if the uart transmit buffer is empty when a serial transfer starts, the uart will drive the value ?80? hexadecimal on it?s miso pin. the spi should only write to the transmit buffer when it is empty. if the trans- mit buffer is written during a serial transfer, the new data will be loaded into the transmit shifter at the end of the current transfer. the slave select function, ssb, is multiplexed on pin p7[3] along with ctsb. when uart2 is configured for spi operation, the ssb function must be selected by setting the u2c0 crd bit to logic ?0? to enable cts/rts functionality and additionally the u2c0 crs bit must be set to logic ?0? to enable cts functionality. if the cts function is not both selected and enabled, the uart2 spi logic will internally hold the ssb signal to the appropriate level dependant on whether the spi is configured for master or slave operation. slave select has various functions depending on the current state of the spi. for an spi configured as a slave, the ssb pin is used to select a slave. for cpha=0, ssb is also used to indicate the start of a trans- mission. since it is used to indicate the start of a transmission, ssb must be toggled high and low between each byte transmitted for the cpha=0 mode for cpha=1 format, ssb may be kept asserted low between transmitted bytes. if ssb is asserted while the spi is configured as a master, a mode fault occurs.
1-143 under development specifications in this manual are tentative and subject to change rev. g serial i/o (3, 4) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer s i/o 3, 4 s i/o 3 and s i/o 4 are exclusive clock-synchronous serial i/os. figure 1.113 shows the s i/oi block diagram and figure 1.114 shows the s i/oi control register. table 1.44 shows the specifications of s i/oi. fig. 1.113. s i/oi block diagram (i = 3,4) s i/oi transmission/reception register (8) s i/o counter i (3) synchronous circuit f 1 f 8 f 32 8 smi5 lsb msb smi2 smi3 smi3 smi1 smi0 p9 0/ clk 3 (p9 5/ clk 4 ) p9 2/ s out3 (p9 6/ s out4 ) p9 1/ s in3 (p9 7/ s in4 ) transfer rate register smi6 note: i = 3, 4. 1/(n +1) 1/2 n = a value set in the s i/o transfer rate register i (0363 16 , 0367 16 ). s i/o i interrupt request data bus i i
1-144 under development specifications in this manual are tentative and subject to change rev. g serial i/o (3, 4) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.114. s i/o 3, 4 related registers si/oi bit rate generator b7 b0 symbol address when reset s3brg 0363 16 indeterminate s4brg 0367 16 indeterminate indeterminate assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r si/oi transmit/receive register b7 b0 symbol address when reset s3trr 0360 16 indeterminate s4trr 0364 16 indeterminate indeterminate transmission/reception starts by writing data to this register. after transmission/reception finishes, reception data is input. w r s i/oi control register (i = 3, 4) (note 1) symbol address when reset sic 0362 16 , 0366 16 40 16 b7 b6 b5 b4 b3 b2 b1 b0 w r description smi5 smi1 smi0 smi3 smi6 smi7 internal synchronous clock select bit transfer direction select bit s i/oi port select bit (note 2) s out i initial value set bit 0 0 : selecting f 1 0 1 : selecting f 8 1 0 : selecting f 32 1 1 : not to be used b1 b0 0 : external clock 1 : internal clock 0 : l output 1 : h output 0 : input-output port 1 : s out i output, clk function bit name bit symbol synchronous clock select bit (note 2) 0 : lsb first 1 : msb first smi2 s out i output disable bit 0 : s out i output 1 : s out i output disable (high impedance) note 1: set "1" in bit 2 of the protection register (000a 16 ) before writing to the s i/oi control register (i = 3, 4). note 2: when using the port as an input/output port by setting the si/oi port select bit (i = 3, 4) to "1" , be sure to set the sync clock select bit to "1" . effective when smi3 = 0 nothing is assigned. write "0" when writing to this bit. when read, the value is "0".
1-145 under development specifications in this manual are tentative and subject to change rev. g serial i/o (3, 4) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.44. specifications of s i/o 3, 4 note 1: n is a value from 00 16 through ff 16 set in the s i/oi transfer rate register (i = 3, 4). note 2: with the external clock selected: before data can be written to the si/oi transmit/receive register (addresses 0360 16 , 0364 16 ), the clki pin input must be in the low state. also, before rewriting the si/oi control register (addresses 0362 16 , 0366 16 ) ? s bit 7 (s outi initial value set bit), make sure the clki pin input is held low. the s i/oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it. note 3: if the internal clock is used for the synchronous clock, the transfer clock signal output, when enabled, item transfer data format transfer clock conditions for interrupt request generation timing select function precaution specifications transfer data length: 8 bits with the internal clock selected (bit 6 of 0362 16 , 0366 16 = ? 1 ? ): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (note 1) to start transmission/reception, the following requirements must be met: - select the synchronous clock (use bit 6 of 0362 16 , 0366 16 ). select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 0362 16 , 0366 16 ). - s out i initial value set bit (use bit 7 of 0362 16 , 0366 16 )= 1. - s i/oi port select bit (bit 3 of 0362 16 , 0366 16 ) = 1. - select the transfer direction (use bit 5 of 0362 16 , 0366 16 ) -write transfer data to si/oi transmit/receive register (0360 16 , 0364 16 ) to use s i/oi interrupts, the following requirements must be met: - clear the si/oi interrupt request bit before writing transfer data to the si/oi transmit/receive register (bit 3 of 0049 16 , 0048 16 ) = 0. rising edge of the last transfer clock. (note 3) lsb first or msb first selection whether transmission/reception begins with bit 0 (lsb) or bit 7 (msb) can be selected. function for setting an s outi initial value selection when using an external clock for the transfer clock, the user can choose the s outi pin output level during a non-transfer time. for details on how to set, see figure 1.112. unlike uart0 ? 2, si/oi (i = 3, 4) is not divided for transfer register and buffer. therefore, do not write the next transfer data to the si/oi transmit/receive register (addresses 0360 16 , 0364 16 ) during a transfer. when the internal clock is selected for the transfer clock, s outi holds the last data for a 1/2 transfer clock period after it finished transferring and then goes to a high-impedance state. however, if the transfer data is written to the si/oi transmit/receive register (addresses 0360 16 , 0364 16 ) during this time, s outi is placed in the high-impedance state immediately upon writing and the data hold time is thereby reduced. i if an internal clock is selected, set the bit rate generator divisor (0363 16 , 0367 16 ) [it is not necessry to start transmit/receive. it is only needed for operation as intended] stops at the "h" state after transmission is completed. with the external clock selected (bit 6 of 0362 16 , 0366 16 = 0): input from the clki terminal (note 2) therefore, stop the synchronous clock immediately when count reaches eight. if selected, the internal clock stops automatically clocking the sio channel. transmit/receive start
1-146 under development specifications in this manual are tentative and subject to change rev. g serial i/o (3, 4) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer functions for setting an s out i initial value when using an external clock for the tranfer clock, the s out i pin output level during a non-transfer time can be set to the high or the low state. figure 1.115 shows the timing chart for setting an s out i initial value. s i/oi operation timing figure 1.116 shows the s i/oi operation timing. fig. 1.115. timing chart for setting s out i's initial value fig. 1.116. s i/oi operation timing chart signal written to the s i/oi transmission/reception register s out i (internal) s out i's initial value set bit (smi7) s out i terminal output s i/oi port select bit (smi3) setting the s out i initial value to h port selection (normal port s out i) d0 (i = 3, 4) initial value = "h" (note) port output d0 (example) with "h" selected for s out i: note: the set value is output only when the external clock has been selected. when initializing s out i, make sure the clki pin input is held "h" level. if the internal clock has been selected or if s out output disable has been set, this output goes to the high-impedance state. s i/oi port select bit smi3 = 0 souti initial value select bit smi7 = 1 (s out i: internal "h" level) s i/oi port select bit smi3 = 0 1 (port select: normal port s out i) s out i terminal = "h" output signal written to the s i/oi register ="l" "h" "l" (falling edge) s out i terminal = outputting stored data in the s i/oi transmission/ reception register d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 (i= 3, 4) (i= 3, 4) hiz hiz (i= 3, 4) 1.5 cycle (max) si/oi internal clock transfer clock (note 1) signal written to the s i/oi register s i/oi output s out i s i/oi input s in i si/oi interrupt request bit note 2 note 1: with the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the s i/oi control register. (i=3,4) (no frequency division, 8-division frequency, 32-division frequency.) note 2: with the internal clock selected for the transfer clock, the s out i pin becomes to the high-impedance state after the transfer finishes. "h" "l" "h" "l" "h" "l" "h" "l" "h" "l" "1" "0"
1-147 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer lcd drive control circuit the M30222 group has the built-in liquid crystal display (lcd) drive control circuit consisting of the following. ? lcd display ram ? segment output enable register ? lcd mode register ? voltage multiplier ? selector ? timing controller ? common driver ? segment driver ? bias control circuit a maximum of 40 segment output pins and 4 common output pins can be used. this allows up to 160 lcd pixels to be controlled. if static drive is enabled, up to 14 of the 40 multiplexed segment pins can be assigned to static drive. the lcd drive control circuit automatically reads the lcd display ram, performs bias and duty ratio control, and displays the data on the lcd panel. the circuit is configured by writing to the lcd mode register, the segment output enable register, the lcd display ram, the lcd frame frequency counter, the lcd expansion register, and the lcd clock divided register. after all these registers are written then the lcd is turned on by setting the lcd enable bit to "1". the lcdram output function allows the lcd segment output pins to be used as a general purpose output pin. this mode is configured by writing to the segment output register to enable the segment function, writing a "00" to the time division select bit and "0" to lcd output enable bit, and setting the lcdram output enable bit to "1". the data that is written to the lcdram bit 4 or 0 will be output on its corresponding segment pin. note that in this mode vl3 & vl2 must be connected to vdd and vl1 must be connected to vss. table 1.45 shows the maximum number of display pixels at each duty ratio. figure 1.117 shows the block diagram of lcd controller / driver. figures 1.118 and 1.119 show the lcd-related registers. table 1.45. maximum number of display pixels at each duty ratio duty ratio 2 3 4 maximum number of display pixels (multiplexed) 80 dots or 8 segment lcd 10 digits 120 dots or 8 segment lcd 15 digits 160 dots or 8 segment lcd 20 digits static drive off off off
1-148 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.117. block diagram of lcd controller/driver data bus low-order bits timing controller 1/8 com 0 com 1 com 2 com 3 v ss v l1 v l2 v l3 seg 3 seg 2 seg 1 seg 0 address 0100 16 address 0101 16 lcdck lcdck count source select bit bias control bit lcd enable bit duty ratio selection bits 2 selector selector selector selector selector selector lcd display ram address 0113 16 p4 6 /seg 38 p4 7 /seg 39 level shift level shift level shift level shift level shift level shift common driver common driver common driver common driver c 1 c 2 voltage multiplier control bit level shift level shift level shift level shift segment driver segment driver segment driver segment driver segment driver segment driver bias control data bus high-order bits v cc lcd output enable bit 1/2 "0" "1" f 32 f c1 lcd frame frequency control counter (8) reload register (8) 1/2 lcd clock divider counter (8) reload register (8) address 0112 selector selector level shift level shift segment driver segment driver p4 5 /seg 37 /lcdclkout p4 4 /seg 36 /syncout segment output enable bit 6 lcd expansion enable bit 0 1 0 1 16
1-149 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.118. lcd related registers (1) lcd mode register symbol address when reset lcdm 0120 16 0x000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function pump lramout duty ratio select bit bias control bit lcd enable bit voltage multiplier control bit lcdt0 lcdt1 bias lcden 0 : 1/3 bias 1 : 1/2 bias 0 : voltage multipler disable 1 : voltage multipler enable (note 2) lcdram output bit 0 : lcd waveform output 1 : lcd data output b1 b0 0 0 : not used 0 1 : 2 duty (use com0, com1) 1 0 : 3 duty (use com0 - com2) 1 1 : 4 duty (use com0 - com3) 0 : lcd off 1 : lcd on note 1: lcdck is a clock for an lcd timing controller. note 2: when voltage multiplier is enabled, bias control bit must be "0". w r lsrc lcdck count source select bit (note 1) nothing is assigned. write "0" when writing to this bit. when read, the value is indeterminate. 0 : f32 1 : fc1 _ _ lcd frame frequency counter symbol address when reset lcdtim 0124 16 indeterminate b7 b0 function w r values that can be set 8 bit timer 00 16 to ff 16 segment output enable register symbol address when reset seg 0122 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function seg01 w r 0 : disable 1 : enable seg02 seg03 seg04 seg05 seg06 seg07 segment output enable bit 1 segment output enable bit 2 segment output enable bit 3 segment output enable bit 4 segment output enable bit 5 segment output enable bit 6 lcd output enable 0 : i/o ports p3 3 1 : segment output seg 27 0 : i/o ports p3 5 to p3 4 1 : segment output seg 28 to seg 29 0 : i/o ports p3 7 to p3 6 1 : segment output seg 30 to seg 31 0 : i/o ports p4 4 to p4 5 1 : segment output seg 36 to seg 37 0 : i/o ports p4 6 to p4 7 1 : segment output seg 38 to seg 39 0 : i/o ports p3 0 to p3 2 1 : segment output seg 24 to seg 26 seg00 segment output enable bit 0 0 : i/o ports p4 0 to p4 3 1 : segment output seg 32 to seg 35 x (note) note: this register must be changed while lcd output enable bit is "0".
1-150 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.119. lcd expansion related register (2) voltage multiplier the voltage multiplier performs threefold boosting. this circuit inputs a reference voltage for boosting from lcd power input pin v l1 . (however, when using a 1/2 bias, supply power to the v l1 and v l2 through an external resistor divider.) to activate the voltage multiplier, choose the segment/port and duty rate, select bias control, and set up the lcd frame frequency counter and lcdck count source using the segment enable register and lcd mode register, then enable the lcd output enable bit (bit 7 at address 0122 16 ) and set the voltage multiplier control bit (bit 4 at address 0120 16 ) to ?1? (= voltage multiplier enabled). when voltage is input to the v l1 pin during operating the voltage multiplier, voltage that is twice as large as v l1 occurs at the v l2 pin, and voltage that is three times as large as v l1 occurs at the v l3 pin. the voltage multiplier control bit (bit 4 of the address 0120 16 ) controls the voltage multiplier. when using the voltage multiplier, apply a voltage equal to or greater than 1.3 v but not exceeding 2.1 v to the v l1 pin before enabling the voltage multiplier control bit. when not using the voltage multiplier, enable the lcd output enable bit and apply an appropriate voltage to the lcd power supply input pins (v l1 to v l3 ). when the lcd output enable bit is disabled, the v l3 pin is connected to v cc internally. lcd expansion register symbol address when reset lexp 0130 16 00 16 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : disable 1 : enable lckpol lexpen lcd clock out and polarity select bit function 0 : sof at rising edge 1 : sof at falling edge lcd expansion enable bit w r nothing is assigned. these bits can neither be set nor reset. when read, the value is indeterminate. lsync lcd syncout initiation bit 0 : no action 1 : initiate sync lstatcnf0 lstatcnf1 lstaten lcd static drive pin configuration select bits 0 0 : seg35 to seg24 static 0 1 : seg35 to seg27 static 1 0 : seg35 to seg32 static 1 1 : do not use lcd static drive enable bit 0 : disable 1 : enable lcd clock divide counter symbol address when reset lcdc 0132 16 indeterminate b7 b0 function w r values that can be set 8 bit timer 00 16 to ff 16 x
1-151 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer common pin and duty control the common pins (com 0 to com 3 ) to be used are determined by the required duty. table 1.47shows the duty control and the common pins used. select duty ratio by the duty ratio select bits (bits 0 and 1 of address 0120 16 ). table 1.46. bias control and applied voltage to vl1 to vl3 bias control and applied voltage to lcd power input pins to the lcd power input pins (v l1 to v l3 ), apply the voltage shown in table 1.46 according to the bias value. select a bias value by the bias control bit (bit 2 of the address 0120 16 ). figure 1.120 is an example of circuit at each bias. fig. 1.120. example of circuit at each bias vl3 vl2 c2 c1 vl1 1/3 bias when using voltage multiplier (vl1<= 2.1v) vl3 vl2 c2 c1 vl1 open open contrast control r1 r2 r3 r1=r2=r3 1/3 bias when not using voltage multiplier vl3 vl2 c2 c1 vl1 open open contrast control r4 r5 r4=r5 1/2 bias vl3 vl2 c2 c1 vl1 open open when selecting lcdram data output (not using lcd panel) bias value 1/3 bias 1/2 bias voltage value vl3 = vlcd vl2 = 2/3 vlcd vl1 = 1/3 vlcd vl3 - vlcd vl2 = vl1 = 1/2 vlcd note: vlcd is the maximum value of supplied voltage for the lcd panel. duty ratio 2 3 4 bit 1 0 1 1 bit 0 1 0 1 common pins used com0, com1 (note 1) com0 to com2 (note 2) com0 to com3 daily ratio select bit note 1: com2 and com3 are open. note 2: com 3 is open. table 1.47. duty ratio control and common pins used
1-152 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer lcd display ram address 0100 16 to 0113 16 is the designated ram for the lcd display. when ?1's" are written to these addresses, the corresponding segments of the lcd display panel are turned on. table 1.48 shows the lcd display ram map. table. 1.48. lcd display ram map 0100 16 0101 16 0102 16 0103 16 0104 16 0105 16 0106 16 0107 16 0108 16 0109 16 010a 16 010b 16 010c 16 010d 16 010e 16 010f 16 0110 16 0111 16 0112 16 0113 16 seg1 seg3 seg5 seg7 seg9 seg11 seg13 seg15 seg17 seg21 seg23 sef25 seg27 seg29 seg31 seg33 seg35 seg37 seg39 seg0 seg2 seg4 seg6 seg8 seg10 seg12 seg14 seg16 seg18 seg20 seg22 seg24 seg26 seg28 seg30 seg32 seg34 seg36 seg38 r o o o o o o o o o o o o o o o o o o o o w o o o o o o o o o o o o o o o o o o o o 7 6 5 4 address bit seg19 3 2 1 0 com 3 3 2 2 1 1 00
1-153 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer lcd drive timing the lcdck timing frequency (lcd drive timing) is generated internally and the frame frequency can be determined with the following equation. the lcdck count source frequency is f c1 (same fre- quency as x cin ) or f 32 (divide-by-32 of x in frequency). figure 1.121 shows the lcd drive waveform (1/2 bias). figure 1.122 shows the lcd drive waveform (1/3 bias). f(lcdck) duty ratio frame frequency= 16 x (lcd frame frequency count value + 1) f(lcdck)= (frequency of count source for lcdck) internal logic lcdck timing 1/4 duty voltage level v l3 v l2 =v l1 v ss v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty v l3 v l2 =v l1 v ss v l3 v ss off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 v l3 v l2 =v l1 v ss v l3 v ss off on off on off on off on com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0 fig. 1.121. lcd drive waveform (1/2 bias)
1-154 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.122. lcd drive waveform (1/3 bias) internal logic lcdck timing 1/4 duty voltage level v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 off on off on off on off on v l3 v l2 v ss v l1 v l3 v l2 v ss v l1 v l3 v ss v l3 v l2 v ss v l1 v l3 v ss com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0
1-155 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.123. lcd drive waveform (static drive) lcd static drive when bit 7 of the lcd expansion register is set, then the static drive function is enabled. the following lcd pins get assigned the static drive function in one of the following groups: seg35 to seg24, seg35 to seg27, or seg35 to seg32. bits 6 and 5 of the lcd expansion register determine the grouping of the static drive pins. all remaining lcd pins retain their normal lcd functions. the waveforms that are output from the static drive pins are shown in figure 1.123. when writing to lcd ram for static operation, write the data to all four bits assigned to that pin. (refer to table 1.50, lcd display ram map). for example, to set static seg 34 on and seg 35 off, write f0 16 to address 0111 16. lcd expansion clock when bit 7 of the lcd expansion register is set, the lcd expansion clock becomes active. in this mode a clock (lcdckout) synchronized to the internal lcd clock can be output from the mcu. the frequency of lcdclkout is set by the lcd clock divided counter and is: f(lcdckout) = (frequency of count source for lcdck) 2 x (lcd clock divided counter + 1) in addition, a synchronization signal (syncout) is output. when the lcd syncout initiation bit is set, this signal will go active low at the beginning of the next lcd frame. refer to figures 1.124 and 1.125. lcdck static com voltage level vl3 vss vl3 vss vl3 vss ["0" written to lcd ram] static seg (pixel off) ["0" written to lcd ram] static seg (pixel on) ["1" written to lcd ram]
1-156 under development specifications in this manual are tentative and subject to change rev. g lcd drive control circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.125. lcd port expansion timing diagram fig. 1.124. lcd port expansion block diagram osc osc 1/32 1/2 lcd ffc 1/(n+1) 1/8 duty ratio 1/4,1/3,1/2 com seg cdc 1/(n+1) 1/2 lcdckout sync generator syncout lcd syncout initiation bit xin xcin v32 lcdck lcd frame freq. d clk q d clk q lcd clock out polarity selection bit lcdck 1 frame next frame com3 active com2 active com1 active com0 active initiate sync syncout
1-157 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capaci- tive coupling amplifier. pins p10 0 to p10 7 , p9 5 , and p9 6 also function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the v ref con- nect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. when set to 10-bit precision, the lower 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. table 1.49 shows the performance of the a-d converter. figure 1.126 shows the block diagram of the a- d converter, and figures 1.127 and 1.128 show the a-d converter-related registers. table 1.49. performance of a-d converter item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock ad (note 2) v cc = 5v f ad /divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) v cc = 3v divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) resolution 8-bit or 10-bit (selectable) absolute precision v cc = 5v without sample and hold function 3lsb with sample and hold function (8-bit resolution) 2lsb with sample and hold function (10-bit resolution) an 0 to an 7 input : 3lsb anex0 and anex1 input (including mode in which external operation amp is connected) : 7lsb v cc = 3v without sample and hold function (8-bit resolution) 2lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8 pins (an 0 to an 7 ) + 2pins (anex0 and anex1) software trigger a-d conversion starts when the a-d conversion start flag changes to ? 1 ? external trigger (can be retriggered) a-d conversion starts when the a-d conversion start flag is ? 1 ? and the ad trg /p9 7 input changes from ? h ? to ? l ? conversion speed per pin without sample and hold function 8-bit resolution: 49 ad cycles, 10-bit resolution: 59 ad cycles with sample and hold function 8-bit resolution: 28 ad cycles, 10-bit resolution: 33 ad cycles note 1: does not depend on use of sample and hold function. note 2: divide the frequency if f(x in ) exceeds 10mh z , and make ad frequency equal to 10mh z . without sample and hold function, set the ad frequency to 250kh z min. with the sample and hold function, set the ad frequency to 2 mhz min. to 1mhz a-d conversion start condition
1-158 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.126. block diagram of a-d converter 1/2 ad 1/2 f ad a-d conversion rate selection (03c1 16 , 03c0 16 ) (03c3 16 , 03c2 16 ) (03c5 16 , 03c4 16 ) (03c7 16 , 03c6 16 ) (03c9 16 , 03c8 16 ) (03cb 16 , 03ca 16 ) (03cd 16 , 03cc 16 ) (03cf 16 , 03ce 16 ) cks1=1 cks0=0 0 0 : normal operation 0 1 : anex0 1 0 : anex1 1 1 : external op-amp mode a-d register 0(16) a-d register 1(16) a-d register 2(16) a-d register 3(16) a-d register 4(16) a-d register 5(16) a-d register 6(16) a-d register 7(16) resistor ladder anex1 anex0 successive conversion register opa1,opa0=0,1 opa0=1 opa1=1 opa1,opa0=1,1 an 0 an 1 an 2 an 3 an 5 an 6 an 7 a-d control register 0 (address 03d6 16 ) a-d control register 1 (address 03d7 16 ) v ref v in data bus high-order data bus low-order v ref an 4 opa1,opa0=0,0 vcut=0 av ss vcut=1 cks0=1 cks1=0 ch2,ch1,ch0=000 ch2,ch1,ch0=001 ch2,ch1,ch0=010 ch2,ch1,ch0=011 ch2,ch1,ch0=100 ch2,ch1,ch0=101 ch2,ch1,ch0=110 ch2,ch1,ch0=111 decoder opa1, opa0 addresses ssh=0 ssh=1 simultaneous sample and hold control comparator comparator
1-159 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.127. a-d converter-related registers (1) a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 (note 2) md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected external op-amp connection mode bit w r b2 b1 b0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 indeterminate. note: if the a-d control register is rewritten during a-d conversion, the conversion result is
1-160 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.128. a-d converter-related registers (2) a-d control register 2 (note) symbol address when reset adcon2 03d4 16 0000xxx0 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function r w note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: ssh must be used ony in conjunction with smp. note 3: user must guarantee a conversion of input "1" after a conversion of input "0" in all modes except sweep modes. a-d register i symbol address when reset adi(i=0 to 7) 03c0 16 to 03cf 16 indeterminate eight low-order bits of a-d conversion result function r w (b15) b7 b7 b0 b0 (b8) during 10-bit mode two high-order bits of a-d conversion result during 8-bit mode when read, the content is indeterminate smp reserved bit always set to ? 0 ? 000 ssh simultaneous sample and hold 0 : disabled 1 : enabled nothing is assigned. write "0" when writing to these bits. when read, the value is "0". nothing is assigned. write "0" when writing to these bits. when read, the value is "0".
1-161 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conversion. table 1.50 shows the specifications of one-shot mode. figure 1.129 shows the a-d con- trol register in one-shot mode. table 1.50. one-shot mode specifications figure 1.129. a-d conversion register in one-shot mode a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0: f ad /4 is selected 1: f ad /2 is selected cks0 w r 0 0 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : vref connected external op-amp connection mode bit 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode w r invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 0 : one-shot mode (note 2) b4 b3 ch0 b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. item specification function the pin selected by the analog input pin select bit is used for one-shot a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag end of a-d conversion (a-d conversion start flag changes ot 0 , except when exter- nal trigger is selected). interrupt request generation timing end of a-d conversion input pin one of an 0 to an 7 as selected reading a-d converter results read a-d register corresponding to selected pin
1-162 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (2) repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conver- sion. table 1.51 shows the specifications of repeat mode. figure 1.130 shows the a-d control register in repeat mode. table 1.51. repeat mode specifications fig. 1.130. a-d conversion register in repeat mode item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 7 as selected reading a-d con- verter results read a-d register corresponding to selected pin a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit w r 01 invalid in repeat mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 1 : repeat mode (note 2) b4 b3 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate.
1-163 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (3) single sweep mode in single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a- d conversion. table 1.52 shows the specifications of single sweep mode. figure 1.131 shows the a- d control register in single sweep mode. fig. 1.131. a-d conversion register in single sweep mode item specification function the pin selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag end of a-d conversion (a-d conversion start flag changes ot 0 , except when exter- nal trigger is selected). interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 and an 3 (4 pins), an 0 and an 5 (6 pins) , or an 0 and an 1 (8 pins) reading a-d converter results read a-d register corresponding to selected pin a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 0 : any mode other than repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 0 invalid in single sweep mode 0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note 2: neither "01" nor "10" can be selected with the external op-amp connection mode bit. table 1.52. single sweep mode specifications
1-164 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 1.53 shows the specifications of repeat sweep mode 0. figure 1.132 shows the a-d control register in repeat sweep mode 0. table 1.53. repeat sweep mode 0 specifications fig. 1.132. a-d conversion register in repeat sweep mode 0 item specification function the pin selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an 0 and an 3 (4 pins), an 0 and an 5 (6 pins) , or an 0 and an 1 (8 pins) reading a-d converter results read a-d register corresponding to selected pin (at any time) a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 0 : any mode other than repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 1 invalid in repeat sweep mode 0 0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither ? 01 ? nor ? 10 ? can be selected with the external op-amp connection mode bit. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1
1-165 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. table 1.54 shows the specifications of repeat sweep mode 1. figure 1.133 shows the a-d control register in repeat sweep mode 1. table 1.54. repeat sweep mode 1 specifications fig. 1.133. a-d conversion register in repeat sweep mode 1 item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit. example: an 0 selected an 0 an 1 an 0 an 2 an 0 an 3 , etc. start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 (1 pin), an 0 and an 1 (2 pins), an 0 and an 2 (3 pins) , an 0 and an 3 (4 pins) reading a-d converter results read a-d register corresponding to selected pin (at any time) a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 1 : repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 1 invalid in repeat sweep mode 1 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither ? 01 ? nor ? 10 ? can be selected with the external op-amp connection mode bit. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1
1-166 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (a) sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to ?1?. when sample and hold is selected, the speed of conversion increases. as a result, a 28 f ad cycle is achieved with 8- bit resolution and 33 f ad with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used. (b) extended analog input pins in one-shot mode and repeat mode, the input via the extended analog input pins anex0 and anex1 can also be converted. when bit 6 of the a-d control register 1 (address 03d716) is ?1? and bit 7 is ?0?, input via anex0 is con- verted. the result of conversion is stored in a-d register 0. when bit 6 of the a-d control register 1 (address 03d716) is ?0? and bit 7 is ?1?, input via anex1 is con- verted. the result of conversion is stored in a-d register 1. (c) external operation amp connection mode in this mode, multiple external analog inputs via the extended analog input pins, anex0 and anex1, can be amplified together by just one operation amp and used as the input for a-d conversion. when bit 6 of the a-d control register 1 (address 03d7 16 ) is ?1? and bit 7 is ?1?, input via an 0 to an 7 is output from anex0. the input from anex1 is converted from analog to digital and the result stored in the corre- sponding a-d register. the speed of a-d conversion depends on the response of the external operation amp. do not connect the anex0 and anex1 pins directly. figure 1.134 is an example of how to connect the pins in external operation amp mode. fig. 1.134. example of external op-amp connection mode analog input external op-amp an 0 an 7 an 1 an 2 an 3 an 4 an 5 an 6 anex1 anex0 resistor ladder successive conversion register comparator
1-167 under development specifications in this manual are tentative and subject to change rev. g a-d converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (6) operation of simultaneous sample and hold mode (ssh) an 1 is sampled exactly the same time as the sampling ofan 0 . the actual conversion occurs when a conver- sion of an 1 is specifically requested. the request can be implicit as a part of a sweep mode or can be explicit by writing an appropriate value to adcon0. the conversion of input 1 must be completed within 33 s after an 0 conversion is started. a-d usage precautions (1) write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 and 7 of a-d control register 2 when a-d conversion is stopped before a trigger occurs. in particular, when the vref connection bit is changed from ?0? to ?1?, start a-d conversion after an elapse of 1 s or longer. (2) when changing a-d operation mode, select analog input pin again. (3) using one-shot mode or single sweep mode read the correspondence a-d register after confirming a-d conversion is finished. (it is known by a-d conver- sion interrupt request bit.) (4) using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 use the undivided main clock as the internal cpu clock. (5) use ssh only in conjunction with smp at 33 s.
1-168 under development specifications in this manual are tentative and subject to change rev. g d-a converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains two independent d-a convert- ers of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 and 1 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. do not set the target port to output mode if d-a conversion is to be performed. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table 1.55 lists the performance of the d-a converter. figure 1.135 shows the block diagram of the d- a converter. figure 1.136 shows the d-a control register. figure 1.137 shows the d-a converter equivalent circuit. table 1.55. performance of d-a converter fig. 1.135. block diagram of d-a converter p9 3 /da 0 p9 4 /da 1 data bus low-order bits d-a register0 (8) r-2r resistor ladder d-a0 output enable bit d-a register1 (8) r-2r resistor ladder d-a1 output enable bit (address 03d8 16 ) (address 03da 16 ) item performance conversion method r-2r resolution 8 bits analog output pin 2 channels
1-169 under development specifications in this manual are tentative and subject to change rev. g d-a converter mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.136. d-a control register fig. 1.137. d-a converter equivalent circuit d-a control register symbol address when reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e d-a register symbol address when reset dai (i = 0,1) 03d8 16 , 03da 16 indeterminate w r b7 b0 function output value of d-a conversion nothing is assigned. write "0" when writing to these bits. if read, the value is "0". v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r da0 msb lsb d-a0 output enable bit "0" "1" d-a0 register0 note 1: the above diagram shows an instance in which the d-a register is assigned 2a 16 . note 2: d-a1 is equivalent to this circuit. note 3: to reduce the current consumption when the d-a converter is not used, set the d-a output enable bit to 0 and set the d-a register ot 00 16 so that no current flows in the resistors rs and 2rs.
1-170 under development specifications in this manual are tentative and subject to change rev. g crc calculation circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer crc calculation circuit the cyclic redundancy check (crc) calculation circuit detects an error in data blocks. the microcom- puter uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. the crc code is set in a crc data register each time one byte of data is transferred to a crc input register after writing an initial value into the crc data register. generation of crc code for one byte of data is completed in two machine cycles. figure 1.138 shows the block diagram of the crc circuit. figure 1.139 shows the crc-related registers. figure 1.140 shows the calculation example using the crc calculation circuit fig. 1.138. block diagram of crc circuit fig. 1.139. crc-related registers eight low-order bits eight high-order bits data bus high-order bits data bus low-order bits crc data register (16) crc input register (8) crc code generating circuit x 16 + x 12 + x 5 + 1 (addresses 03bd 16 , 03bc (address 03be 16 ) 16 ) symbol address when reset crcd 03bd 16 , 03bc 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register w r crc calculation result output register function values that can be set 0000 16 to ffff 16 symbo address when reset crcin 03be 16 indeterminate b7 b0 crc input register w r data input register function values that can be set 00 16 to ff 16
1-171 under development specifications in this manual are tentative and subject to change rev. g crc calculation circuit mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.140. calculation example using the crc calculation circuit b15 b0 (1) setting 0000 16 crc data register crcd [03bd 16 , 03bc 16 ] b0 b7 b15 b0 (2) setting 01 16 crc input register crcin [03be 16 ] 2 cycles after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 1189 16 stores crc code b0 b7 b15 b0 (3) setting 23 16 crc input register crcin [03be 16 ] after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 0a41 16 stores crc code the code resulting from sending 01 16 in lsb first mode is (1000 0000). thus the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000) x 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. thus the crc code becomes (1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary in the crc operation circuit built in the m16c, switch between the lsb side and the msb side of the input-holding bits, and carry out the crc operation. also switch between the msb and lsb of the result as stored in crc data. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb msb lsb msb 98 1 1 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1
under development specifications in this manual are tentative and subject to change rev. g i/o ports mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer 1-172 programmable i/o ports there are 55 programmable i/o ports: p3 to p10 (excluding p5, p8 3 and p8 7 ). each port can be set indepen- dently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p8 3 is an input-only port and has no built-in pull-up resistance. p7 0 and p7 1 do not have pull up resistors. figures 1.141 to 1.143 show the programmable i/o ports. figure 1.144 shows the i/o pins. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a converter), they function as outputs regardless of the contents of the direction registers. when pins are to be used as the outputs for the d-a converter, do not set the direction registers to output mode. see the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figure 1.145 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these registers corresponds one for one to each i/o pin. (2) port registers figure 1.146 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (3) pull-up control registers figure 1.147 shows the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input.
1-173 under development specifications in this manual are tentative and subject to change rev. g i/o ports mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.141. programmable i/o ports (1) p3, p4 port latch direction register data bus segment output dq ck ? 1 ? ? 1 ? interface logic level shift circuit lcd drive timing port/segment port on/off v l3 /v cc v l2 /v cc v l3 /v cc v l2 /v ss timer a overflow p6 2 , p6 6, port latch pull-up selection direction register data bus p7 7 , p8 2 , p8 6 , p9 1 , p9 7 port latch pull-up selection direction register data bus input respective peripheral functions p6 0 , p6 1, p6 3 , p6 4 , p6 5 , p6 7, p7 2 , p7 3 , p7 4 , p7 5 , p7 6 , p7 7 , p8 0 , p8 1 , p8 2 , ? 1 ? output p9 0 , p9 2-4
under development specifications in this manual are tentative and subject to change rev. g i/o ports mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer 1-174 fig. 1.142. programmable i/o ports (2) direction register port latch data bus input respective peripheral functions ? 1 ? output p7 0 to p7 1 nmi interrupt input data bus p8 3 p10 0 to p10 5 port latch pull-up selection direction register data bus analog input pull-up selection direction register port latch analog input data bus input to respective peripheral functions p9 5 , p9 6, p10 6 , p10 7 ? 1 ? output (note) note : symbolizes a parasitic diode. do not apply a voltage higher than vcc to each port.
1-175 under development specifications in this manual are tentative and subject to change rev. g i/o ports mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.143. programmable i/o ports (3) fig. 1.144. i/o pins port latch pull-up selection direction register data bus analog output p 9 3 , p 9 4 v ss v l3 v l2 v l1 the gate input signal of each transistor is controlled by the lcd duty ratio and the bias value. com 0 to com 3 , seg 0 to seg 23 d-a output enabled d-a output enabled input to respective peripheral functions note : symbolizes a parasitic diode. do not apply a voltage higher than vcc to each pin. (note) cnv ss cnv ss signal input reset reset signal input note : symbolizes a parasitic diode. (note) (note) do not apply a voltage higher than vcc to each pin.
under development specifications in this manual are tentative and subject to change rev. g i/o ports mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer 1-176 fig. 1.145. direction register fig. 1.146. port register bit symbol bit name function r w pdi_0 port pi 0 direction register pdi_1 port pi 1 direction register pdi_2 port pi 2 direction register pdi_3 port pi 3 direction register pdi_4 port pi 4 direction register pdi_5 port pi 5 direction register pdi_6 port pi 6 direction register pdi_7 port pi 7 direction register port pi direction register (note) b7 b6 b5 b4 b3 b2 b1 b0 symbol pdi (i = 3 to 10, except 5 and 8) address 03e7 16 , 03ea 16 , 03ee 16 , 03ef 16 , 03f3 16 , 03f6 16 when reset 00 16 note: set bit 2 of protect register (address 000a 16 to ? 1 ? before rewriting to the port p9 direction register . 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 3, 4, 6, 7, 9, 10) b7 b6 b5 b4 b3 b2 b1 b0 port p8 direction register bit symbol bit name function r w pd8_0 port p8 0 direction register pd8_1 port p8 1 direction register pd8_2 port p8 2 direction register pd8_4 port p8 4 direction register pd8_5 port p8 6 direction register pd8_6 port p8 7 direction register nothing is assigned. write ? 0" when writing to this bit. when read, the value is indeterminate. 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) symbol pd8 address 03f2 16 when reset 00x00000 2 nothing is assigned. write ? 0" when writing to this bit. when read, the value is indeterminate. _ _ bit symbol bit name function r w pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register port pi register b7 b6 b5 b4 b3 b2 b1 b0 symbol pi (i = 3 to 10, except 5 and 8) address 03e5 16 , 03e8 16 , 03ec 16 , 03ed 16 , 03f1 16 , 03f4 16 when reset indeterminate data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ? l ? level data 1 : ? h ? level data (note) (i = 3, 4, 6, 7, 9, 10) bit symbol bit name function r w p8_0 port p8 0 register p8_1 port p8 1 register p8_2 port p8 2 register p8_3 port p8 3 register p8_4 port p8 4 register p8_5 port p8 5 register p8_6 port p8 6 register nothing is assigned. write ? 0 ? when writing to this bit. when read, the value is indeterminate. port p8 register b7 b6 b5 b4 b3 b2 b1 b0 symbol p8 address 03f0 16 when reset data is input and output to and from each pin by reading and writing to and from each corresponding bit except for p8 3 ) 0 : ? l ? level data 1 : ? h ? level data x0000000 16 note: because p7 and p7 1 are n-channel open drain ports, the data are high impedance.
1-177 under development specifications in this manual are tentative and subject to change rev. g i/o ports mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.147. pull-up register pull-up control register 0 symbol address when reset pur0 03fc 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high pull-up control register 1 symbol address when reset pur1 03fd 16 00 16 (note 1) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up pu11 p4 4 to p4 7 pull-up pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 2, pull-up (note 2) pu17 p7 4 to p7 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high note 1: when the v cc level is being impressed to the cnv ss terminal, this register becomes to 02 16 when reset (pu11 becomes to ? 1 ? ). pull-up control register 2 symbol address when reset pur2 03fe 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 2 pull-up pu21 p8 4 to p8 6 pull-up (except p8 3 ) pu22 p9 0 to p9 3 pull-up pu23 p9 4 to p9 7 pull-up pu24 p10 0 to p10 3 pull-up pu25 p10 4 to p10 7 pull-up nothing is assigned. the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high x xxx xx o o o o o o nothing is assigned. write "0" when writing to these bits. o o p7 3 write "0" when writing to these bits. when read, the value is indeterminate. nothing is assigned. write "0" when writing to these bits note 2: because p7 0 and p7 1 are n-channel open-drain ports, the pull up is not available.
under development specifications in this manual are tentative and subject to change rev. g i/o ports mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer 1-178 unused pins table 1.56. example of connections for unused pins fig. 1.148. example of connections for unused pins note: with external clock input to xin pin. pin name connection ports p3 to p10 (excluding p5, p8 3 , p8 7 ) after setting for input mode, enable internal pull-up resistors or connect every pin to vss cia a resistor. or, after setitng for output mode, leave these pins open. xout (note) open nmi connect to vcc via pull-up resistor avcc connect vcc avss, v ref connect to vss c1, c2 open vl2, vl3 connect to vcc vl1 connect to vss cnvss connect to vss via pull-up resistor com 0 to com 3 open seg 0 to seg 23 open port p3 to p10 (except for p5, p8 3 ) (input mode) (input mode) (output mode) nmi x out av cc av ss v ref microcomputer v cc v ss open open vl3 vl2 vl1 open cnvss c 1 , c 2 open open open xcout com 0 to com 3 seg 0 to seg 23
1-179 under development specifications in this manual are tentative and subject to change rev. g electrical characteristics mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer electrical characteristics table 1.57. absolute maximum ratings symbol parameter condition rated value unit vcc supply voltage vcc=avcc -0.3 to 6.5 v avcc analog supply voltage vcc=avcc -0.3 to 6.5 v v i input voltage reset , , p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 , vref, xin, cnvss (mask rom version) -0. 3 to vcc + 0.3 v vl1 -0.3 to vl2 v vl2 vl1 to vl3 v vl3 vl2 to 6.5 v p7 0 , p7 1 , c1, c2, cnvss (flash memory version) -0.3 to 6.5 v v o output voltage p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 2 , p8 4 to p 8 6 , p9 0 to p9 7 , xout , -0.3 to vcc + 0.3 v p3 0 to p3 7 , p4 0 to p4 7 when output port -0.3 to vcc v when segment output -0.3 to vl3 v p7 0 , p7 1, cnvss (mask rom ver- sion) -0.3 to 6.5 v pd power dissipation ta=25 o c 300 mw topr operating ambient temperature -40 to 85 o c tstg storage temperature -65 to 150 o c
1-180 under development specifications in this manual are tentative and subject to change rev. g electrical characteristics mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.58. recommended operating conditions (referrenced to vcc = 2.7 to 5.5v at ta = -20 to 85c or - 40 to 85c (note 3) unless othewise specified) symbol parameter standard unit min typ. max vcc supply voltage 2.7 5.0 5.5 v avcc analog supply voltage vcc v vss supply voltage 0v avss analog supply voltage 0v v ih high input voltage xin, reset , cnvss, byte, p3 1 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 0.8 vcc vcc v p70, p71 0.8 vcc 6.5 v v il low input voltage xin, reset , cnvss, p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 ,p7 0 to p7 7 , p8 0 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 0 0.2 vcc v i oh (peak) high peak output current (note 2) p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 2 , p8 4 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 -10.0 ma i oh (avg) high average output current (note 1) p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 2 , p8 4 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 -5.0 ma i ol (peak) low peak output current (note 2) p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 2 , p8 4 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 10.0 ma i ol (avg) low average output current (note 1) p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 2 , p8 4 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 5.0 ma f(xin) main clock input oscillation frequency (note 3) no wait vcc=tbd to 5.5v 0 16 mhz vcc=2.7v to tbd0 tbdmhz with wait vcc=tbd to 5.5v 0 16 mhz vcc=2.7v to tbd0 tbdmhz f(xcin) subclock oscillation frequency 32.768 50 khz note 1: the average output current is the mean value within 100ms. note 2: the total i ol (peak) and i oh (peak) fo ports p3, p4, p6, p7, p8 0 to p8 2 , p8 4 to p8 6 , p9 and p10 must be 80 ma max. note 3: relationship between main clock oscillation frequency and supply voltage. main clock input oscillation frequency (mask rom version, flash memory 5v version, no wait) 16.0 tbd 0.0 2.7 tbd 5.5 operating maximum frequency [mh z ] supply voltage [v] (bclk: no division) tbd main clock input oscillation frequency (mask rom version, flash memory 5v version, with wait) 16.0 tbd 0.0 2.7 tbd 5.5 operating maximum frequency [mh z ] supply voltage [v] (bclk: no division) tbd
1-181 under development specifications in this manual are tentative and subject to change rev. g electrical characteristics mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.59. electrical characteristics (referenced to vcc = 5v, vss = 0v at ta = 25c, f(xin) = 16mhz unless otherwise specified. symbol parameter measuring condition standard unit min typ. max v oh high output voltage p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 2 , p8 4 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 i oh =-5ma 3.0 v v oh high output voltage p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 2 , p8 4 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 i oh =-200 a4.7v v oh high out- put voltage xout high power i oh =-1ma 3.0 v low power i oh =-0.5ma 3.0 v high output voltage xcout high power with no load applied 3.0 v low power with no load applied 1.6 v v ol low output voltage p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 2 , p8 4 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 i ol =-5ma 2.0 v v ol low output voltage p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 2 , p8 4 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 i ol =-200 a0.45v v ol low output voltage xout high power i ol =-1ma 2.0 v low power i ol =-0.5ma 2.0 v low output voltage xcout high power with no load applied 0 v low power with no load applied 0 v v t + - v t - hysteresis ta0in to ta4in, ta0in to tb3in, int0 to int5 , ad trg , cts0 , cts1 , clk0, clk1, ta2out to ta4out, nmi , ki0 to ki4 0.2 0.8 v v t + - v t - hysteresis reset 0.2 1.8 v i ih high input current xin, reset , cnvss, p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 v i =5v 5.0 a i il low input current xin, reset , cnvss, p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 6 , p9 0 to p9 7 , p10 0 to p10 7 v i =0 - 5 . 0 a r pullup pull-up resistance p3 0 to p3 7 , p4 0 to p4 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 2 , p8 4 to p8 6, p9 0 to p9 7 , p10 0 to p10 7 v i =0v 30.0 50.0 167.0 k ? r f(xin) feedback resistance xin 1.0 m ? r f(xcin) feedback resistence xcin 6.0 m ? v ram ram retention voltage when clock is stopped 2.0 v icc power supply current mask rom versions f(xin) =16 mhz square wave, no division 30.0 50.0 ma flash memory 5v version f(xin) =16 mhz square wave, no division 35.0 50.0 ma mask rom versions f(xcin) =32 khz square wave 90.0 a flash memory 5v version f(xcin) =32 khz square wave 8.0 ma f(xcin) =32 khz when a wait instruction is executed 4.0 a ta =25 o c when clock is stopped 1.0 a ta = 85 o c when clock is stopped 20.0
1-182 under development specifications in this manual are tentative and subject to change rev. g electrical characteristics mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.60. a-d conversion characterisitics (referenced to vcc = avcc + vref = 5v, vss = avss = 0v at ta = 25c, f(xin) = 16mhz unless otherwise specified) table 1.61. d-a conversion characteristics (referenced to vcc = 5v, vss = avss = 0v, vref = 5v at ta = 25c, f(xin) = 16mhz unless otherwise specified) symbol parameter measuring condition standard unit min. typ. max. _ resolution vref = vcc 10 bits _ absolute accuracy sample & hold function not available vref = vcc = 5v +/-3 lsb sample & hold function available (10 bit) vref = vcc = 5v an 0 to an 7 input +/-3 lsb anex0, anex1 input, external op-amp connection mode +/-7 lsb sample & hold function available (8 bit) vref = vcc = 5v +/-2 lsb r ladder ladder resistence vref = vcc 10 40 k ? t conv conversion time (10 bit) 3.3 s t conv converstion time (8 bit) 2.8 s t samp sampling time 0.3 s vref reference voltage 2 vcc v v ia analog input voltage 0 vref v note: this applies when using one d-a converter, with the d-a register. the unused d-a converter is set to 00 16 . the a-d converter s ladder resistance is not included. when the vref is disconnected at the a-d control register, ivref is sent. symbol parameter measuring condition standard unit min. typ. max. _ resolution 8 bits _ absolute accuracy 1.0 % t su settling time 3 s r o output resistance 4 10 20 k ? i vref reference power supply input current (note) 1.5 m
1-183 under development specifications in this manual are tentative and subject to change rev. g electrical characteristics mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.62 external clock input table 1.63. timer a input (counter input in event counter mode) table 1.64. timer a input (gating input in timer mode) table 1.65. timer a input (external trigger input in one-shot timer mode) timing requirements (referenced to vcc = 5v, vss = 0v at ta = 25 c unless otherwise stated) symbol parameter standard unit min. max. t c external clock input cycle time 62.5 ns t w (h) external clock input high pulse width 25 ns t w (l) external clock input low pulse width 25 ns t r external clock rise time 15 ns t f external clock fall time 15 ns symbol parameter standard unit min. max. t c (ta) taiin input cycle time 100 ns t w (tah) taiin input high pulse width 40 ns t w (tal) taiin input low pulse width 40 ns symbol parameter standard unit min. max. t c (ta) taiin input cycle time 400 ns t w (tah) taiin input high pulse width 200 ns t w (tal) taiin input low pulse width 200 ns symbol parameter standard unit min. max. t c (ta) taiin input cycle time 200 ns t w (tah) taiin input high pulse width 100 ns t w (tal) taiin input low pulse width 100 ns
1-184 under development specifications in this manual are tentative and subject to change rev. g electrical characteristics mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.66. timer a input (external trigger input in pulse width modulation mode) table 1.67. timer a input (up/down input in event counter mode) table 1.68. timer b input (counter input in event counter mode) table 1.69. timer b input (pulse period measurement mode) symbol parameter standard unit min. max. t w (tah) taiin input high pulse width 100 ns t w (tal) taiin input low pulse width 100 ns symbol parameter standard unit min. max. t c (up) taiout input cycle time 2000 ns t w (uph) taiout input high pulse width 1000 ns t w (upl) taiout input low pulse width 1000 ns t su (up-tin) taiout input setup time 400 ns t h (tin-up) taiout input hold time 400 ns symbol parameter standard unit min. max. t c (tb) tbiin input cycle time (counted on one edge) 100 ns t w (tbh) tbiin input high pulse width (counted on one edge) 40 ns t w (tbl) tbiin input low pulse width (counted on one edge) 40 ns t c (tb) tbiin input cycle time (counted on both edges) 200 ns t w (tbh) tbiin input high pulse width (counted on both edges) 80 ns t w (tbl) tbiin input high pulse width (counted on both edges) 80 ns symbol parameter standard unit min. max. t c (tb) tbiin input cycle time 400 ns t w (tbh) tbiin input high pulse width 200 ns t w (tbl) tbiin input low pulse width 200 ns
1-185 under development specifications in this manual are tentative and subject to change rev. g electrical characteristics mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.70. timer b input (pulse width measurement mode) table 1.71. a-d trigger input table 1.72 serial i/o table 1.73. external interrupt inti inputs timing requirements (referenced to vcc = 5v, vss = 0v at ta = 25 c unless otherwise stated) symbol parameter standard unit min. max. t c (tb) tbiin input cycle time 400 ns t w (tbh) tbiin input high pulse width 200 ns t w (tbl) tbiin input low pulse width 200 ns symbol parameter standard unit min. max. t c (tb) tbiin input cycle time 400 ns t w (tbh) tbiin input high pulse width 200 ns t w (tbl) tbiin input low pulse width 200 ns symbol parameter standard unit min. max. t c (ck) clki input cycle time 200 ns t w (ckh) clki input high pulse width 100 ns t w (ckl) clki input low pulse width 100 ns t d (c-q) txdi output delay time 80 ns t h (d-c) txdi hold time 0 ns t su (d-c) rxdi input setup time 30 ns t h (c-d) rxdi input hold time 90 ns symbol parameter standard unit min. max. t w (inh) inti input high pulse width 250 ns t w (inl) inti input low pulse width 250 ns
1-186 under development specifications in this manual are tentative and subject to change rev. g description (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer flash memory the M30222 (flash memory version) has an internal new dinor (divided bit line nor) flash memory that can be rewritten with a single power source. three flash memory modes are available that read, program, and erase: parallel i/o and standard serial i/o modes that flash memory manipulates using a programmer, and a cpu rewrite mode that flash memory can manipulate using the central processing unit (cpu). each mode is detailed in the following pages. the flash memory is divided into several block as shown in figure 1.149 so that memory can be erased one block at a time. each block has a lock bit to enable or disable execution of an erase or program operation, allowing data in each block to be protected. in addition to the ordinary user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the users application system. this boot rom area can be rewritten in only parallel i/o mode. outline performance table 1.74 shows the outline performance of the M30222 (flash memory version). table 1.74. outline performance note: the boot area contains a standard serial i/o control mode control program stored in it when it is shipped from the factory. this area can be erassed and programmed in paralell i/o mode only. item performance erase/write voltage 2.7 to 5.5v flash memory operation mode three modes: cpu rewrite, parallel i/o, standard serial erase block division user rom area see fig. 1.149 boot rom area one division (8 kbytes) (note) program method uses word units erase method collective erase/block erase program/erase control method program/erase control by software command number of commands 8 program/erase count 100 rom code protect parallel i/o and standard serial modes are supported.
1-187 under development specifications in this manual are tentative and subject to change rev. g description (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.149. block diagram of flash memory version 7d000 16 7e000 16 7ffff 16 80000 16 bffff 16 block 8 : 4 kbytes block 7 : 64 kbytes block 6 : 64 kbytes block 5 : 64 kbytes block 4 : 32 kbytes block 3 : 24 kbytes block 3 : 24 kbytes block 2: 4 k byte block 1: 4 k byte boot rom area: 8 kbytes reserved c0000 16 d0000 16 e0000 16 f0000 16 f8000 16 fe000 16 ff000 16 fffff 16 user rom area: note 1: the boot rom area can be rewritten in only parallel input/output mode. (access to any other areas is inhibited. note 2: to specify a block, use the maximum address in the block that is an even address.
1-188 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer cpu rewrite mode in cpu rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). only the user rom area shown in figure 1.149 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite control pro- gram must be transferred to ram memory before it can be executed. microcomputer mode and boot mode normal microcomputer mode is entered when the microcomputer is reset with pulling cnvss pin low. in this case, the cpu starts executing the control program in the user rom area. when the microcom- puter is reset and both the cnvss pin and p7 4 (ce) pin are pulled high, the cpu starts operating using the control program in the boot rom area (program start address is c0000 16 , 7d000 16 ). this mode is called the "boot" mode. the control program for cpu rewrite mode must be written into the user rom or boot rom area beforehand. (if the control program is written into the boot rom area, standard serial i/o mode be- comes unusable.) see figure 1.149 for details about the boot rom area. block address block addresses refer to the maximum even address of each block. these addresses are used in the block erase command. outline performance in the cpu rewrite mode, the cpu erases, programs, and reads the internal flash memory as in- structed by software commands. this rewrite control program must be transferred to internal ram before it can be executed. the cpu rewrite mode is accessed by writing "1" for the cpu rewrite mode select bit (bit 1 in address 034b4 16 ). software commands are accepted once the mode is accessed. in the cpu rewrite mode, software commands are used to write and read data into even-numbered addresses ("0" for byte address a0) in 16-bit units. always write 8-bit software comands into even- numbered address. commands are ignored with odd-numbered addresses. use software commands to control program and erase operations. whether a program or erase op- eration has terminated normally or in error can be verified by reading the status register. figure 1.150 shows the flash memory control register.
1-189 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.150 flash memory control registers bit 0 is the ry/by status flag used exclusively to read the operating status of the flash memory. during programming and erase operations, it is "0". otherwise, it is "1". bit 1 is the cpu rewrite mode select bit. when this bit is set to "1", the M30222 accesses the cpu rewrite mode. software commands are accepted once the mode is accessed. in cpu rewrite mode, the cpu becomes unable to access the internal flash memory directly. therefore, the control program that sets this bit must be executed out of ram. to set this bit to "1", it is necessary to write "0" and then write "1" in succession. the bit can be set to "0" by only writing a "0". bit 2 is the cpu rewrite mode entry flag. this bit can be read to check whether the cpu rewrite mode has been entered or not. bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. when the cpu rewrite mode select bit is "1" for this bit resets the control circuit. to release the reset, it is necessary to set this bit to "0". if the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. figure 1.151 shows a flowchart for setting/releas- ing the cpu rewrite mode. bit 4 is the flash memory protect bit. the blocks are write protected when this bit is "0". the write protect is disabled when the bit is "1". the mcu must be in cpu rewrite mode for this bit to have any effect. to set this bit to "1", it is necessary to write "0" and then write "1" in succession. flash memory control register symbol address when reset fmcr 03b4 16 xxxx0001 2 b7 b6 b5 b4 b3 b2 b1 b0 ry/by status flag fmcr0 bit symbol bit name function 0: busy (being written or erased) 1: ready cpu rewrite mode select bit (note 1) 0: normal mode (software commands invalid) 1: cpu rewrite mode (software commands acceptable) fmcr1 0: normal mode 1: cpu rewrite mode flash memory reset bit (note 2) 0: normal operation 1: reset fmcr2 fmcr3 note 1: for this bit to be set to 1, the user needs to write a "0" and then a "1" to it in succession. use the control program in ram for write to this bit. nothing is assigned. when write, set "0". when read, values are indeterminate. cpu rewrite mode entry flag fmcr4 write protect bit (note 1) 0: write protected 1: write enabled note 2: for this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession when the cpu rewrite mode selection bit is = "1". o o o o o r w
1-190 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer figure 1.151. cpu rewrite mode set/reset flowchart precautions on cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. (1) operation speed during cpu rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 0006 16 and bits 6 and 7 at address 0007 16 ): 5.0 mhz or less when wait bit (bit 7 at address 0005 16 ) = 0 (no wait state) 10.0 mhz or less when wait bit (bit 7 at address 0005 16 ) = 1 (one wait state) (2) instruction inhibited against use the instructions listed below cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory: und instruction, into instruction, jmps instruction. jsrs instruction, and brk instruction (3) interrupts inhibited against use the nmi, address match, and watchdog timer interrupts cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory. if interrupts have their vector in the variable vector table, they can be used by transferring the vector into the ram area. (4) reset if the mcu is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. set a 5 ms wait to release the reset operation. also, when the reset has been released, the program execute start address is automatically set to 07e000 16 , therefore program so that the execute start address of the boot rom is 07e000 16 . single-chip mode or boot mode (note 1) set processor mode register (note 2) jump to transferred control program in ram (subsequent operations are executed by control program in this ram) transfer cpu rewrite mode control program to internal ram start execute read array command or reset flash memory by setting flash memory reset bit (by writing ? 1 ? and then ? 0 ? in succession) (note 4) using software command execute erase, program, or other operation write ? 0 ? to cpu rewrite mode select bit set cpu rewrite mode select bit to ? 1 ? (by writing ? 0 ? and then ? 1 ? in succession) (note 3) end check cpu rewrite mode entry flag *1 *1 program in rom program in ram note 1: apply 5v +/- 10% to cnvss pin by confirmation of cpu rewrite mode entry flag when starting operation with single-chip mode. note 2: during cpu rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 0006 16 and bits 6 and 7 at address 0007 16 : 5 mhz or less when wait bit (bit 7 at address 0005 16 ) = "0" (without internal access wait state); 10 mhz or less when wait bit (bit 7 at address 0005 16 ) = "1" (with internal access wait state) note 3: for cpu rewrite mode sleect bit to be set to "1", the user needs to write a "0" and then a"1" to it in succession. when not in this mode, it is not in "1". this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. note 4: before exiting the cpu, rewrite mode after completing erase or program operation, always be sure to execute a read array command to reset the flash memory.
1-191 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer software commands table 1.75 lists the software commands available with the M30222 (flash memory version). after setting the cpu rewrite mode select bit to 1, write a software command to specify an erase or program operation. note that when entering a software command, the upper byte (d 8 to d 15 ) is ig- nored. the content of each software command is explained below. read array command (ff 16 ) the read array mode is entered by writing the command code "ff 16 " in the first bus cycle. when an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (d 0 ?d 15 ), 16 bits at a time. the read array mode is retained intact until another command is written. read status register command (70 16 ) when the command code "70 16 " is written in the first bus cycle, the content of the status register is read out at the data bus (d 0 ?d 7 ) by a read in the second bus cycle. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the error bits of the status register after they have been set. these bits indicate that operation has ended in an error. to use this command, write the command code "50 16 " in the first bus cycle. table 1.75. list of software commands (cpu rewrite mode) note 1: when a software command is input, the high-order byte of data (d15:d8) is ignored. note 2: srd = status register data note 3: wa = write address, wd = write data (16 bits) note 4: ba = block address (enter the maximum address of each block that is an even address) note 5: x denotes a given even address in the user rom. note 6: lock bit output on data bit 6 commands (note 1) cycle no. 1st bus cycle 2nd bus cycle mode address data (d7:d0) mode address data (d7:d0) read 1 write x (note 5) ffh id codes 2 write x 90h read ia id status regiser read 2 write x 70h read x srd (note 2) status register clear 1 write x 50h word program 2 write x 40h write wa (note 3) wd (note 3) auto block erase 2 write x 20h write ba (note 4) d0h erase 2 write x 20h write x 20h (erase all unlocked blocks) 2 write x a7h write x d0h lock bit status read 2 write x 71h read ba (note 4) (d6)(note 6) lock bit program 2 write x 77h write ba (note 4) d0h
1-192 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer program command (40 16 ) program operation starts when the command code "40 16 " is written in the first bus cycle. then, if the address and data to program are written in the second bus cycle, program operation (data programming and verification) will start. whether the write operation is completed can be confirmed by reading the status register or the ry/by status flag. when the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (d 0 ?d 7 ). the status register bit 7 (sr7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is written. the ry/by status flag is 0 during write operation and 1 when the write operation is completed as is the status register bit 7. at program end, program results can be checked by reading the status register. figure 1.152 shows an example of a program flowchart. fig. 1.152. program flowchart start write 40 16 read status register no yes sr4= 0 program complete no yes write address and data sr7=1? or ry/by=1 program error
1-193 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer erase all command (20 16 /20 16 ) (erases all blocks regardless of lock status) by writing the command code "20 16 " in the first bus cycle and the confirmation command code "20 16 " in the second bus cycle that follows, the system starts erase all blocks (erase and erase verify). whether the erase all blocks command is terminated can be confirmed by reading the status register or the ry/by status flag. when the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. the status register bit 7 (sr7) is set to "0" at the same time the erase operation starts and is returned to "1" upon completion. the read status register mode remains active until the read array command (ff 16 ) is written. the boot block area is not affected by this command. the ry/by status flag is "0" during erase operation and "1" when the erase operation is completed as is the status register bit 7. at erase all blocks end, erase results can be checked by reading the status register. for details, refer to the section where the status register is detailed. block erase command (20 16 /d0 16 ) by writing the command code "20 16 " in the first bus cycle and the confirmation command code "d0 16 " in the second bus cycle that follows the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. whether the block erase operation is completed can be confirmed by reading the status register or the ry/by status flag. at the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to "0" at the same time the clock erase operation starts and is returned to "1" upon completion of the block erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ). the ry/by status flag is "0" during block erase operation and "1" when the block erase operation is completed as is the status register bit 7. after the block erase operation is completed, the status register can be read out to know the result of the block erase operation. for details, refer to the section where the status register is detailed.
1-194 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.153. erase flowchart erase all unlocked blocks command (a7 16 /d0 16 ) by writing the command code "a7 16 " in the first bus cycle and the confirmation command code "d0 16 " in the second bus cycle that follows, the system starts erase all unlocked blocks (erase and erase verify). whether the erase all unlocked blocks command is terminated can be confirmed by reading the status register or the ry/by status flag. when the erase all unlocked blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. the status register bit 7 (sr7) is set to "0" at the same time the erase operation starts and is returned to "1" upon completion of the erase operation. the read status register mode remains active until the read array command (ff 16 ) is written. the ry/by status flag is "0" during erase operation and "1" when the erase operation is completed as is the status register bit 7. at erase all blocks end, erase results can be checked by reading the status register. for details, refer to the section where the status register is detailed. figure 1.153 shows an example of a block erase flowchart. start write 20 16 /a7 16 read status register no yes sr5= 0 erase completed no yes block address sr7=1? or ry/by=1 erase error 20 16 : all blocks a7 16 : only unlocked blocks 20 16 : chip erase a7 16 : block/chip erase write 20 16 /d0 16
1-195 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer lock bit program command (77 16 /d0 16 ) this command is available only when the lock bit is enabled. for cpu rewrite mode bit 4 must be a "1". in parallel mode wpb must be a "0". by writing the command code ("77 16 ") in the first bus cycle and the confirmation code ("d0 16 ") and block address in the second cycle the lock bit can be programmed for the block specified. the lock bit protects the block against erase during the erase all unlocked blocks command. the status of the lock bit can be read by issuing the lock bit status read command. figure 1.154 is an example of a lockbit program flowchart. fig. 1.154. lock bit program flowchart start write 77 16 no yes sr4= 0? lock bit program completed no yes write 77 16 block address ry/by lock bit program error status flag =1?
1-196 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.155. lockbit status read flowchart lock bit status read command (71 16 ) this command is available only when the lock bit is enabled. for cpu rewrite mode bit 4 must be a "1". in parallel mode wpb must be a "0". by writing the command code ("71 16 ") in the first bus cycle and reading the block address and data bit 6 in the second cycle, the value of the lock bit for that block address can be read. a "0" means that the block is locked. a "1" means that the block is unlocked. figure 1.155 is an example of a lockbit status read flowchart. start write 71 16 blocks locked no yes enter block address (note) d6 = 0? blocks not locked note: data bus bit 6
1-197 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer data protect function (block lock) each block in figure 1.156 has a nonvolatile lock bit to specify that the block be protected (locked) against erase or write. the lock bit program command is used to set the lock bit to 0 (locked). the lock bit of against each block can be read out using the read lock bit status command. whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register 0's lock bit disable bit is used. (1) when the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status (lock bit data). blocks whose lock bit data = 0 are locked, so they are disabled against erase/write. on the other hand, the blocks where the lock bit data =1 are not locked, they're enabled for erase/write. (2) when the lock bit disable bit =1, all blocks are unlocked regardless of the lock bit data, so they are enabled for erase/write. in this case, the lock bit data, that is 0 (locked), is set to 1 (unlocked) after erase, so that the lock bit lock is removed. fig. 1.156. block diagram of user area 7d000 16 7e000 16 bffff 16 block 8 : 4 kbytes block 7 : 64 kbytes block 6 : 64 kbytes block 5 : 64 kbytes block 4 : 32 kbytes block 3 : 24 kbytes block 3 : 24 kbytes block 2: 4 k byte block 1: 4 k byte c0000 16 d0000 16 e0000 16 f0000 16 f8000 16 fe000 16 ff000 16 fffff 16 flash memory size flash memory start address 260 kbytes 7d000 c0000 16 16
1-198 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer status register the status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. it can be read in the following ways. (1) by reading an arbitrary address from the user rom area after writing the read status register command (70 16 ) (2) by reading an arbitrary address from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ). also, the status register can be cleared by writing the clear status register command (50 16 ). after a reset, the status register is set to "80 16 ". table 1.76. definition of each bit in status register each bit in this register is explained below. sequencer status (sr7) after power-on, the sequencer status is set to 1 (ready). the sequencer status indicates the operating status of the device. this status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status informs the operating status of erase operation to the cpu. when an erase error occurs, it is set to 1. the erase status is reset to 0 when cleared. program status (sr4) the program status informs the operating status of write operation to cpu. when a write error occurs, it is set to 1. the program status is reset to 0 when cleared. when an erase command is in error (which occurs if the command entered after the block erase command (20 16 ) is not the confirmation command (d0 16 ), both the program status and erase status (sr5) are set to 1. when the program status or erase status = 1, the following commands entered by the command write are not accepted. also, in one of the following cases, both sr4 and sr5 are set to 1 (command sequence error): (1) when the valid command is not entered correctly (2) when the data entered in the second bus cycle of lock bit program (77 16 /d0 16 ), block erase (20 16 /d0 16 ), or erase all unlocked blocks (a7 16 /d0 16 ) is not the d0 16 or ff 16 . however, if ff 16 is entered, read array is assumed and the command that has been set up in the first busy cycle is cancelled. each srd bit status name definition 10 sr7 (bit 7) write state machine (wsm) status ready busy sr6 (bit 6) reserved _ _ sr5 (bit 5) erase status terminated in error terminated normally sr4 (bit 4) program status terminated in error terminated normally sr3 (bit 3) reserved _ _ sr2 (bit 2) over write back status terminated in error terminated normally sr1 (bit 1) over erase status terminated in error terminated normally sr0 (bit 0) reserved _ _
1-199 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.157 full status check flowchart and remedial procedure for errors over write back status (sr2) the over write back status informs the operating status of the write back operation during an erase sequence. when a write back error occurs, sr5 and sr2 are set to "1". the over write back status is reset to "0" when cleared. over erase status (sr1) the over erase status informs the operating status of the erase operation during an erase sequence. when an erase error occurs, sr5 and sr1 are set to "1". the over erase status is reset to "0" when cleared. if sr5 or sr4 bits = "1", the program, erase all blocks, and block erase commands are not accepted. before executing these commands, execute the clear status register command (50 16 ) and clear the status register. bits sr2 and sr1 give more information on the reason for failure. also, if any commands are not correct, both sr5 and sr4 are set to 1. full status check by performing full status check, it is possible to know the execution results of erase and program operations. figure 1.157 shows a full status check flowchart and the action to be taken when each error occurs. read status register sr4=1 and sr 5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error (page or lock bit) no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. if an error occurs, the block in error cannot be used. note: when one of sr5 to sr4 is set to 1, none of the page program, block erase, or erase all blocks commands is accepted. execute the clear status register command (50 16 ) before executing these commands.
1-200 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.158. rom code protect control addrsss functions to inhibit rewriting flash memory version to prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a rom code protect function for use in parallel i/o mode and an id code check function for use in standard serial i/o mode. rom code protect register the rom code protect function prevents reading out or modifying the contents of the flash memory during parallel i/o mode. figure 1.158 shows the rom code protect control address (0fffff 16 ). it is located at the hightest 8 bits of the 32 bit reset vector. if one of the pair of rom code protect bits is set to "0", rom code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. rom code protect is implemented in two levels. if level 2 is selected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to "00", rom code protect is turned off, so that the contents of the flash memory version can be read out or modified. once rom code protect is tuned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/o or some other mode to rewrite the contents of the rom code protect reset bits. symbol address when reset romcp 0fffff 16 ff 16 rom code protect level 2 set bit (note 1, 2) 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect control address bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: protect removed 01: protect set bit effective 10: protect set bit effective 11: protect set bit effective 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect reset bit (note 3) rom code protect level 1 set bit (note 1) romcp2 romcr romcp1 b3 b2 b5 b4 b7 b6 note 1: when rom code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. reserved bit note 2: when rom code protect level 2 is turned on, rom code readout by a shipment inspection lst tester, etc., is also inhibited. note 3: the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, because these bits cannot be changed in paralell input/ output mode, they need to be rewritten in one of the two other modes. always set this bit to "1" 1 1
1-201 under development specifications in this manual are tentative and subject to change rev. g cpu rewrite mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer id code check function use this function in standard serial i/o mode. when the contents of the flash memory are not blank, the id code sent from the peripheral unit is compared with the id code written in the flash memory to see if they match: if the id codes do not match, the commands sent from the peripheral unit are not accepted. the id code consists of 8-bit data, the areas of which, beginning with the first byte, are 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . write a pro- gram which has had the id code preset at these addresses to the flash memory. figure 1.159 shows the storage location for the code addresses. fig. 1.159. code address storage reset watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector to 0fffff 16 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address romcp
1-202 under development specifications in this manual are tentative and subject to change rev. g parallel i/o mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer parallel i/o mode the parallel i/o mode inputs and outputs the software commands, addresses and data needed to oper- ate (read, program, erase, etc.) the internal flash memory. figure 1.160 shows the pin layout for flash paralell mode. table 1.77 is adescription of pin functions in paralell i/o mode. use an exclusive programmer supporting M30222 (flash memory version). refer to the instruction manual of each programmer make for the detail of use. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure 1.149 can be rewritten. both areas of flash memory can be operated on in the same way. program and block erase operations can be performed in the user rom area. the user rom area and its blocks are shown in figure 1.149. the boot rom area is 8 kbytes in size. in parallel i/o mode, it is located at addresses 07e000 16 through 07fff 16 . make sure program and block erase operations are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 8 kbyte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the mitsubishi factory. therefore, using the device in standard serial input/output mode, you do not need to write to the boot rom area.
1-203 under development specifications in this manual are tentative and subject to change rev. g parallel i/o mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.160. pin connections for flash parallel mode 91 85 86 87 88 89 90 92 93 94 95 96 97 98 99 81 82 83 84 100 40 2 1 seg30/p36 vl3 p74/ta2out/w 46 24 vl1 com2 p107/an7/int7 p106/an6/int6 p105/an5 p104/an4 p103/an3 p102/an2 p101/an1 avss p100/an0 vref avcc p97/adtrg/led7/sin4/int3 p75/ta2in/w 23 p76/ta3out/int4 22 p77/ta3in/int4 21 p80/ta4out/int5 /u 20 p82/int0 19 p81/ta4in/int5 /u 18 p83/nmi 17 vcc 16 xin 15 vss 14 xout 13 reset 12 11 p85/xcin 10 cnvss 9 p86/ int1 8 p90/tb0in/ int2 /clk3 7 p91/tb1in/sin3 6 p92/tb2in/sout3 5 p93/da0/tb3in 4 p94/da1/tb4in 3 p95/anex0/clk4 p96/anex1/sout4 seg31/p37 45 seg32/p40 44 seg33/p41 43 seg34/p42 42 seg35/p43 41 seg36/p44 seg37/p45 39 38 37 p60/cts0 /rts0 /ki0 36 p61/clk0/ki1 35 p62/rxd0/ki2 34 p63/txd0/ki3 33 p64/cts1 /rts1 /cts0 /clks1/ki4 32 p65/clk1/ki5 M30222fg p67/txd1/ki7 29 p70/txd2/sda/ta0out 28 p71/rxd2/scl/ta0in/tb5in 27 p72/clk2/ta1out/v 26 p73/cts2 /rts2 /ta1in/v 25 p66/rxd1/ki6 30 seg26/p32 50 seg27/p33 49 seg28/p34 48 seg29/p35 47 com1 com0 c2 c1 p84/xcout seg38/p46/rtp0 seg39/p47/rtp1 vl2 79 80 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 52 53 54 55 56 51 31 seg19 seg18 seg17 seg16 seg15 vdc seg14 vss seg13 seg12 seg11 seg10 seg09 seg08 seg07 seg06 seg05 seg04 seg03 seg02 seg01 seg00 com3 seg25/p31 seg24/p30 seg23 seg22 seg21 seg20 vcc mode set-up method signal value cnvss reset vcc vss vss vcc cnvss reset sclk vss a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 ext pulse rp we ce oe bsel byte ry/by osc a3 a4 a5 a2 a1 a0 a19 a18 a17 a16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 iwp 0.1 f capacitor
1-204 under development specifications in this manual are tentative and subject to change rev. g parallel i/o mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.77. description of pin function in parallel i/o mode pin name signal name i/o function vcc, vss power input i apply 2.7-5.5 v to vcc pin and o v to vss pin cnvss cnvss i connect 0.1 f capacitor from vcc to vss reset reset input i connect to vss xin/xout clock input i no connection required for parallel flash programming avcc, avss analog power supply i connect avss to vss and avcc to vcc p3 0 address bit 4 i address bit 4 p3 1 address bit 5 i address bit 5 p3 2 to p3 7 input port p3 no connection required for parallel flash programming p4 0 to p4 7 input port p4 no connection required for parallel flash programming p6 0 input port p6 no connection required for parallel flash programming p6 1 sclk i connect to vss p6 2 to p6 5 input port p6 no connection required for parallel flash programming p6 7 osc o flash oscillator p7 0 ry/by o ready / busy signal p7 1 byte i byte mode control mode p7 2 bsel input i boot select mode p7 3 oe input i output enable pin p7 4 ce input i chip enable pin p7 5 we input i write enable pin p7 6 extpulse i external pulse for test modes p7 7 rp i deep power down pin p8 0 address bit 6 i address bit 6 p8 1 address bit 7 i address bit 7 p8 2 address bit 8 i address bit 8 p8 3 address bit 9 i address bit 9 p8 4 address bit 10 i address bit 10 p8 5 address bit 11 i address bit 11
1-205 under development specifications in this manual are tentative and subject to change rev. g parallel i/o mode (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer pin name signal name i/o function p9 0 address bit 12 i address bit 12 p9 1 address bit 13 i address bit 13 p9 2 address bit 14 i address bit 14 p9 4 to p9 5 input port 9 no connection required for parallel flash programming p9 7 input port 9 no connection required for parallel flash programming vref a/d vref voltage i connect a/d reference voltage to vcc p10 0 to p10 7 input port p10 input h , l or leave open vl1 to vl3 lcd power supply i connect vl1 to vss; vl2 and vl3 to vcc c1 to c2 lcd condenser leave open com0 to com2 com ports leave open com3 iwp i write protect pin seg0 to seg15 data bits 0 - 15 i/o data bits 0 - 15 seg16 address bit 16 i address bit 16 seg17 address bit 17 i address bit 17 seg18 address bit 18 i address bit 18 seg19 address bit 19 i address bit 19 seg20 address bit 0 i address bit 0 seg21 address bit 1 i address bit 1 seg22 address bit 2 i address bit 2 seg23 address bit 3 i address bit 3
1-206 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, program erase, etc.) the internal flash memory. there are two standard serial i/o modes that require a purpose specific peripheral unit. ? serial i/o mode 1 is synchronized ? serial i/o mode 2 is as asynchronized the standard serial i/o mode is different from the parallel i/o mode because it uses the cpu rewrite mode to control flash memory rewrite, rewrite data input and so on. it is started when the reset is re- leased. this is done when the p5 0 (ce) pins is ?h? level, the p5 5 (epm) pin ?l? level and the cnvss pin ?h? level. in an ordinary command mode, the cnvss pin is set to ?l? level. this control program is written in the boot rom area when the product is shipped from mitsubishi. please note that the standard serial i/o mode cannot be used if the boot rom area is rewritten in parallel i/o mode. in standard serial i/o mode, only the user rom area (see figure 1.181) can be rewritten. the boot rom cannot. also, a 7-byte id code is used. when there is data in the flash memory, commands sent from the periph- eral unit are not accepted unless the id code matches. figure 1.161 shows the pin connections for the standard serial i/o mode. serial data i/o uses uart1 and transfers the data serially in 8-bit units. standard serial i/o switches between mode 1 and mode 2 according to the level of clk1 pin when the reset is released. serial i/o mode 1 to use standard serial i/o mode 1, set the clk1 pin to ?h? level and release the reset. the operation uses the four uart1 pins clk1, rxd1, txd1 and rts1 (busy). the clk1 pin is the transfer clock input pin through which an external transfer clock is input. the txd1 pin is for cmos output. the rts1 (busy) pin outputs an ?l? level when ready for reception and ?h? level when reception starts. serial i/o mode 2 to use standard serial i/o mode 2, set the clk1 pin to ?l? level and release the reset. the operation uses the two uart1 pins rxd1 and txd1.
1-207 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer overview of standard serial i/o mode 1 (clock synchronous) in standard serial i/o mode 1, software commands, addresses and data are input and output between the mcu and peripheral units (serial programmer, etc.) using 4-wire clock-synchronous serial i/o (uart1). standard serial i/o mode 1 is engaged by releasing the reset with the p5 6 (clk1) pin ?h? level. in reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the clk 1 pin, and are then input to the mcu via the rxd 1 pin. in transmis- sion, the read data and status are synchronized with the fall of the transfer clock, and output from the txd 1 pin. the txd 1 pin is for cmos output. transfer is in 8-bit units lsb first. when busy, such as during transmission, reception, erasing or program execution the rts 1 (busy) pin is ?h? level. accordingly, always start the next transfer after the rts 1 (busy) pin is ?l? level. also, data and status register in memory can be read after inputting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register.
1-208 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.161. pin connections for flash serial i/o mode 91 85 86 87 88 89 90 92 93 94 95 96 97 98 99 81 82 83 84 100 40 2 1 seg30/p36 vl3 p74/ta2out/w 46 24 vl1 com2 p107/an7/int7 p106/an6/int6 p105/an5 p104/an4 p103/an3 p102/an2 p101/an1 avss p100/an0 vref avcc p97/adtrg/led7/sin4/int3 p75/ta2in/w 23 p76/ta3out/int4 22 p77/ta3in/int4 21 p80/ta4out/int5 /u 20 p82/int0 19 p81/ta4in/int5 /u 18 p83/nmi 17 v cc 16 xin 15 vss 14 xout 13 reset 12 11 p85/xcin 10 cnvss 9 p86/int1 8 p90/tb0in/int2 /clk3 7 p91/tb1in/sin3 6 p92/tb2in/sout3 5 p93/da0/tb3in 4 p94/da1/tb4in 3 p95/anex0/clk4 p96/anex1/sout4 seg31/p37 45 seg32/p40 44 seg33/p41 43 seg34/p42 42 seg35/p43 41 seg36/p44 seg37/p45 39 38 37 p60/cts0 /rts0 /ki0 36 p61/clk0/ki1 35 p62/rxd0/ki2 34 p63/txd0/ki3 33 p64/cts1 /rts1 /cts0 /clks1/ki4 32 p65/clk1/ki5 M30222fg p67/txd1/ki7 29 p70/txd2/sda/ta0out 28 p71/rxd2/scl/ta0in/tb5in 27 p72/clk2/ta1out/v 26 p73/cts2 /rts2 /ta1in/v 25 p66/rxd1/ki6 30 seg26/p32 50 seg27/p33 49 seg28/p34 48 seg29/p35 47 com1 com0 c2 c1 p84/xcout seg38/p46/rtp0 seg39/p47/rtp1 vl2 79 80 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 52 53 54 55 56 51 31 seg19 seg18 seg17 seg16 seg15 vdc seg14 vss seg13 seg12 seg11 seg10 seg09 seg08 seg07 seg06 seg05 seg04 seg03 seg02 seg01 seg00 com3 seg25/p31 seg24/p30 seg23 seg22 seg21 seg20 vcc mode set-up method signal value cnvss reset vcc vss vcc vss vcc cnvss reset busy sclk rxd txd 0.1 f capacitor
1-209 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.78. pin connections for serial i/o mode pin name signal name i/o function vcc, vss power input i/o apply 2.7 to 5.5 v to vcc pin and 0 v to the vss pin cnvss cnvss i connect to vcc reset reset input i connect vss xin/xout clock input i connect a ceramic resonator or crystal oscillator between xin and xout pins. to input an externally generated clock, input it to xin and open xout pin avcc, avss analog power supply i connect avss to vss and avcc to vcc p3 0 to p3 7 input port p3 i/o input h , l , or leave open p4 0 to p4 7 input port p4 i/o input h , l , or leave open p6 0 busy i/o standard serial mode 1: busy signal output pin standard serial mode 2: monitors program operation check. p6 1 sclk i/o standard serial mode 1: serial clock input pin standard serial mode 2: input l p6 2 rxd input i/o serial data input pin p6 3 txd output i/o serial data output pin p6 4 to p6 7 input port p6 i/o input h , l , or leave open p7 0 to p7 7 input port p7 i/o input h , l , or leave open p8 0 to p86 input port p8 i/o input h , l , or leave open p9 0 to p9 7 input port p9 i/o input h , l , or leave open p10 0 to p10 7 input port p10 i/o input h , l , or leave open vref a/d vref voltage i input a/d reference voltage vl1 to vl3 lcd power supply i/o connect vl1 to vss; vl2 and vl3 to vcc when lcd is not used c1 to c2 lcd condenser i/o connect a condenser between c1 and c2 when using lcd voltage multiplier. leave open when not used. com0 to com3 com ports i/o leave open vdc voltage down converter 0.1 f capacitor connect to vss
1-210 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer software commands table 1.79 lists software commands. in the standard serial i/o mode 1, erase operations, programs and reading are controlled by transferring software commands via the rxd0 pin. software commands are explained here below. table 1.79. software commands (standard serial i/o mode 1) note 1: the shaded areas indicate a transfer from flash mcu to serial programmer. all other data is transferred from programmer to mcu. note 2: srd to status register data. srd1 refers to status register 1 data. note 3: all commands are accepted if the reset vector is blank. control command 2nd byte 3rd byte 4th byte 5th byte 6th byte when id is not verified 1 page read ff 16 address (middle) address (high) data output data output data output data output to 259th byte not acceptable 2 page program 41 16 address (middle) address (high) data input data input data input data input to 259th byte not acceptable 3 block erase 20 16 address (middle) address (high) d0 16 not acceptable 4 erase all unlocked blocks a7 16 d0 16 not acceptable 5 read status register 70 16 srd output srd output acceptable 6 clear status register 50 16 not acceptable 7 read lock bit status 71 16 address (middle) address (high) lock bit data output not acceptable 8 lock bit program 77 16 address (middle) address (high) d0 16 not acceptable 9 lock bit enable 7a 16 not acceptable 10 lock bit disable 75 16 not acceptable 11 id check function f5 16 address (low) address (middle) address (high) id size id1 id7 acceptable 12 download function fa 16 size (low) size (high) check sum data input as required not acceptable 13 version data output function fb 16 version data output version data output version data output version data output version data output version data output to 9th byte acceptable 14 boot rom area output function fc 16 address (middle) address (high) data output data output data output data output to 259th byte not acceptable 15 read check data fd 16 crc data (low) crc data (high) not acceptable 16 word read fe 16 address (low) address (middle) address (high) not acceptable 17 word program 40 16 address (low) address (middle) address (high) not acceptable 18 exit b9 16 acceptable
1-211 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.162. timing for page read (1) page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ?ff 16 ? command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 ?d 7 ) for the page (256 bytes) specified with address a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. data0 data255 clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 ff 16 (2) page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) transfer the "41 16 " command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 ?d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. when reception setup for the next 256 bytes ends, the rts0 (busy) signal changes from the "h" to the "l" level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. fig. 1.163. timing for the page program clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 41 16 data0 data255
1-212 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.164. timing for block erase (3) block erase command this command erases the data in the specified block. execute the block erase command as explained here following: (1) transfer the ?20 16 ? command code with the 1st byte. (2) transfer addresses a8 to a15 and a16 to a23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code ?d0 16 ? with the 4th byte. with the verify command code, the erase operation will start for the specified block in the flash memory. write the highest address the specified block for addresses a 8 to a 23 . when block erasing ends, the rts0 (busy) signal changes from the ?h? to the ?l? level. after block erase ends, the result of the block erase operation can be known by reading the status register. for more informa- tion, see the section on the status register. (4) erase all unlocked blocks command this command erases the content of all blocks. execute the erase all unlocked blocks command explained below. (1) transfer the "a7 16 " command code with the 1st byte. (2) transfer the verify command code "d0 16 " with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. when block erase ends, the rts0 (busy) signal changes from "h" to "l". the result of the erase operation can be known by reading the status register. each block can be erase protected with the lock bit. for more information, see the data protection function section. fig.1.165. timing for erasing all unlocked blocks a 8 to a 15 a 16 to a 23 20 16 d0 16 clk0 rxd0 txd0 rts0(busy) clk1 rxd1 txd1 rts1(busy) a7 16 d0 16 (m16c transmit data) (m16c receive data)
1-213 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.166. timing for reading the status register (5) read status register command this command reads status information. when the "70 16 " command code is sent with the 1st byte, the con- tents of the status register (srd) specified with the 2nd byte and the contents of status register 1 (srd1) specified with the 3rd byte are read. fig. 1.167. timing for clearing the status register (6) clear status register command this command clears the bits (sr4 - sr5) which are set when the status register operation register operation ends in error. when the "5016" command code is sent with thefirst byte, the aforementioned bits are cleared. when the clear status register operation ends, the rts0 (busy) signal changes from the "h" to the "l" level. srd output srd1 output clk0 rxd0 txd0 rts0(busy) 70 16 clk0 rxd0 txd0 rts0(busy) 50 16
1-214 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (7) read lock bit status command this command reads the lock bit status of the specified block. execute the lock bit program command as explained here following. (1) transfer the "71 16 " command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) the lock bit data of the specified block is output with the 4th byte. write the highest address of the speci- fied block for address a 8 to a 23 . fig. 1.168. timing for reading lock bit status (8) lock bit program command this command writes "0" (lock) for the lock bit of the specified block. execute the lock bit program command as explained here following. (1) transfer the "77 16 " command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes. (3) transfer the verify command code "d0 16 " with the 4th byte. with the verify command code, "0" is written for the lock bit of the specified block. write the highest address of the specified block for address a 8 to a 23 . when writing ends, rts0 (busy) signal changes from the "h" to "l". lock bit status can be read with the read lock bit status command. for information on the lock bit function an reset procedure, see the data protection function section. a 8 to a 15 a 16 to a 23 77 16 d0 16 clk1 rxd1 txd1 rts1(busy) (m16c transmit data) (m16c receive data) fig. 1.169. timing for the lock bit program a 8 to a 15 a 16 to a 23 71 16 clk0 rxd0 txd0 rts0(busy) (m16c transmit data) (m16c receive data) d0 16
1-215 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (9) lock bit enable command this command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. the command code "7a 16 " is sent with the 1st byte of the serial transmission. this command only enables the lock bit function; it does not set the lock bit itself. fig. 1.170. timing for enabling the lock bit (10) lock bit disable command this command disables the lock bit. the command code "7516" is sent with the 1st byte of the serial transmis- sion. this command only disables the lock bit function; it does not set the lock bit itself. however, if an erase command is executed after executing the lock bit disable command, "0" (locked) lock bit data is set to "1" (unlocked) after the erase operation ends. in any case, after the reset is cancelled, the lock bit is enabled. fig. 1.171. timing for disabling the lock bit clk0 rxd0 txd0 rts0(busy) 75 16 (m16c receive data) (m16c transmit data) clk0 rxd0 txd0 rts0(busy) 7a 16 (m16c receive data) (m16c transmit data)
1-216 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.172. timing for the id check (11) id check this command checks the id code. execute the boot id check command as explained here following. (1) transfer the "f5 16 " command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code with the 2nd, 3rd and 4th bytes respectively. (3) transfer the number of data sets of the id code with the 5th byte. (4) the id code is sent with the 6th byte onward, starting with the 1st byte of the code. id size id1 id7 clk0 rxd0 txd0 rts0(busy) f5 16 df 16 ff 16 0f 16 id code when the flash memory is not blank, the id code sent from the peripheral units and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the peripheral units is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0ffef 16 , 0ffff3 16 , 0fff7 16 , and 0ffffb 16 . write a program into the flash memory, which already has the id code set for these addresses. fig. 1.173. id code storage addresses reset watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0fffff 16 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address to
1-217 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.174. timing for download (12) download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) transfer the "fa 16 " command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte on- ward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. (13) version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) transfer the ?fb 16 ? command code with the 1st byte. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. fig. 1.175. timing for version information output fa 16 program data program data data size (high) data size (low) check sum clk0 rxd0 txd0 rts0(busy) fb 16 'x' 'v' 'e' 'r' clk0 rxd0 txd0 rts0(busy)
1-218 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (15) read crc data this command reads the crc data that confirms that the write data sent with the page program command was successfully received. (1) transfer the "fd 16 " command code with the 1st byte. (2) the crc data (low) is received with the 2nd byte and the crc data (high) with the 3rd byte. to use this command, first execute the command and then initialize the check data. next, execute the page program command the required number of times. after the read crc command is executed again, the crc data for all the read data that was sent with the page program command is read. the crc data is the result of crc operation of write data. fig. 1.177. timimg for the read crc data fig. 1.176. timing for boot rom area ouput (14) boot rom area output command this command outputs the control program stored in the boot rom area in one page blocks (256 bytes). execute the boot rom area output command as explained here following. (1) transfer the "fc 16 " command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 -d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. data0 data255 clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 fc 16 clk1 rxd1 txd1 rts1(busy) fd 16 (m16c receive data) (m16c transmit data) crc data (low) crc data (high)
1-219 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (16) word read program this command reads the word from the specific address. to execute the word read command: (1) transfer the "fe 16 " command code with the 1st byte. (2) transfer the 3 byte address starting with the a0-a8 with the next 3 bytes. (3) the mcu transfers the byte at the specific address. (4) the mcu transfers the byte at the specific address +1. note: the specified address may be odd or even (a0=0 or 1) and be any value withing the 1m address space. fig. 1.178. timimg for the word read program (17) word program this command writes the word in the flash memory. to execute the word program command: (1) transfer the "40 16 " with the 1st byte. (2) transfer the 3 byte address starting with the a0-a8 with the next 3 bytes. (3) transfer the 1st half of the word to be written in the lower address (a0=0). (4) transfer the 2nd half of the word to be written in the higher address (a0=1). note: the specified address must be even (a0=0). figure 1.179. timing for the word program low fe 16 clk0 rxd0 txd0 rts0(busy) address address middle address high 1st half 2nd half of word of word low 40 16 clk0 rxd0 txd0 rts0(busy) address address middle address high 1st half 2nd half of word of word
1-220 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (18) exit command this command does a software reset by writing a "1" to bit 3 of the processor mode register 0. to execute the exit command: (1) transfer "b9 16 " with the 1st byte. (2) transfer the confirm command code "d0 16 " in the 2nd byte. if the cnvss line is low, the mcu will reset in normal mode and begin execution of the user code. if cnvss is high, the mcu will reset back into boot mode and begin execution at 7e000 16 again. figure 1.180.. timing for the exit command clk1 rxd1 txd1 rts1(busy) b9 16 d0 16
1-221 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer data protection (block lock) each of the blocks in figure 1.181 have a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. a block is locked (writing "0" for the lock bit) with the lock bit program command. also, the lock bit of any block can be read with the read lock bit status command. block lock disable enable is determined by the status of the lock bit itself and executing status of the lock bit disable and lock bit commands. (1) after the reset has been cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). blocks with a "0" lock bit data are locked and cannot e erased or written in. on the other hand, blocks with a "1" lock bit data are unlocked and can be erased or written in. (2) after the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit data status and can be erased or written in. in this case, lock bit data that was "0" before the block was erased is set to "1" (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. fig. 1.181. block in the user area 7d000 16 7e000 16 bffff 16 block 8 : 4 kbytes block 7 : 64 kbytes block 6 : 64 kbytes block 5 : 64 kbytes block 4 : 32 kbytes block 3 : 24 kbytes block 3 : 24 kbytes block 2: 4 k byte block 1: 4 k byte c0000 16 d0000 16 e0000 16 f0000 16 f8000 16 fe000 16 ff000 16 fffff 16 flash memory size flash memory start address 260 kbytes 7d000 c0000 16 16 user rom area
1-222 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.80. status register (srd) sequencer status (sr7) after power-on, the sequencer status is set to 1 (ready). the sequencer status indicates the operating status of the device. this status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status reports the operating status of the automatic erase operation. if an erase error occurs, it is set to ?1?. when the erase status is cleared, it is set to ?0?. program status (sr4) the program status reports the operating status of the auto write operation. if a write error occurs, it is set to ?1?. when the program status is cleared, it is set to ?0?. status register (srd) the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table 1.80 gives the definition of each status register bit. after clearing the reset, the status register outputs ?80 16 ?. each srd bit status name definition 10 sr7 (bit 7) write state machine (wsm) status ready busy sr6 (bit 6) reserved _ _ sr5 (bit 5) erase status terminated in error terminated normally sr4 (bit 4) program status terminated in error terminated normally sr3 (bit 3) reserved _ _ sr2 (bit 2) reserved _ _ sr1 (bit 1) reserved _ _ sr0 (bit 0) reserved _ _
1-223 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer table 1.81. status register definitions for srd1 status register 1 (srd1) status register 1 indicates the status of serial communications, results from id checks, and results from check sum comparisons. it can be read after the srd by writing the read status register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table 1.81 gives the definition of each status register 1 bit. "00 16 " is output when power is turned on and the flag status is mainteined even after the reset. boot update completed bit (sr15) this flag indicates whether the control program was downlaoded to the ram or not, using the download function. check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program is downloaded for execution using the download function. id check completed bits (sr11 and sr10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. srd 1 bits status name definition 10 sr15 (bit 7) boot update complete bit update completed not completed sr14 (bit 6) reserved _ _ sr13 (bit 5) reserved _ _ sr12 (bit 4) checksum match bit match no match sr11 (bit 3) sr10 (bit 2) id check completed bits 0 0 not verified 0 1 verification mismatch 1 0 reserved 1 1 verified sr9 (bit 1) data receive time out time out normal operation sr8 (bit 0) reserved _ _
1-224 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer fig. 1.182. full status check flowchart and remedial procedure for errors full status check results from executed erase and program operations can be known by running a full status check. figure 1.182 shows a flowchart of the full status check and explains how to remedy errors which occur. read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error no end (block erase program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. execute the read lock bit status command (71 16 ) to see if the block is locked. after removing lock, execute write operation in the same way. if the error still occurs, the page in error cannot be used. note: when one of sr5 to sr3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. execute the
1-225 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 1 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer example circuit application for the standard serial i/o modes 1 and 2 figure 1.183 shows a circuit application for the standard serial i/o modes 1 and 2. control pins will vary according to programmer, therefore see the peripheral unit manual for more information. fig. 1.183. example circuit application for serial i/o modes 1 and 2 rts0(busy) clk0 r x d0 t x d0 cnvss clock input busy output data input data output m16c/ M30222 flash memory version (1) control pins and external circuitry will vary according to programmer. for more information, see the programmer manual. nmi cnvss reset reset
1-226 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer standard serial i/o mode 2 (clock asynchronized) in standard serial i/o mode 2, software commands, addresses and data are input and output between the mcu and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial i/o (uart0). standard serial i/o mode 2 is engaged by releasing the reset with the p6 1 (clk 0 ) pin "l" level. the txd 0 pin is for cmos output. data transfer is in 8-bit units with lsb first, 1 stop bit and parity off. after the reset is released, connections can be established at 9,600 bps when initial communications (figure 1.183) are made with a peripheral unit. however, this requires a main clock with a minimum 2 mhz input oscillation frequency. baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. however, communication errors may occur because of the oscillation frequency of the main clock. if errors occur, change the main clock's oscillation frequency and the baud rate. after executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. data and status registers in memory can be read after transmitting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following are explained initial communications with peripheral units, how frequency is identified and software commands. initial communications with peripheral units after the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation frequency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (figure 1.83). (1) transmit "b0 16 " from a peripheral unit. if the oscillation frequency input by the main clock is 10 mhz, the mcu with internal flash memory outputs the "b0 16 " check code. if the oscillation frequency is anything other than 10 mhz, the mcu does not output anything. (2) transmit "00 16 " from a peripheral unit 16 times. (the mcu with internal flash memory sets the bit rate generator so that "00 16 " can be successfully received.) (3) the mcu with internal flash memory outputs the "b0 16 " check code and initial communications end success- fully (see note). initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. also, the baud rate at the end of initial communications is 9,600 bps. note: if the peripheral unit cannot receive "b0 16 " successfully, change the oscillation frequency of the main clock.
1-227 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer identifying frequency when "00 16 " data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 10 mhz). the highest speed is taken from the first 8 transmis- sions and the lowest from the last 8. these values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. baud rate cannot be attained with some operating frequencies. table 1.182 gives the operation frequency and the baud rate that can be attained for. table 1.82. operation frequency and baud rate figure 1.83. peripheral unit and initial communication + : communications possible - : communications not possible operation frequency (mhz) baud rate 9600 bps baud rate 19200 bps baud rate 38400 bps baud rate 57600 bps 16 ++++ 12 + + + - 11 + + + - 10 + + - - 8++-+ 7.3728 + + + + 6+++- 5++-- 4.5 + + - + 4.194304 + + + - 4++-- 3.58 + + + - 3+++- 2 +--- "b0 16 " "00 16 " if the oscillation frequency input by the main clock is 10 or 16 mhz, the mcu outputs "b0 16 ". if other than 10 or 16 mhz, the mcu does not output anything. peripheral unit mcu with internal flash memory (3) transfer check code "b0 16" "b0 16 " "b0 16 " "00 16 " "00 16 " "00 16 " (1) transfer "b0 16 " (2) transfer "00 16" 16 times 1st 2nd at least 15ms transfer interval 15th 16th the bit rate generator setting completes (9600 bps) reset
1-228 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer software commands table 1.183 lists software commands. in the standard serial i/o mode 2, erase operations, programs and reading are controlled by transferring software commands via the rxd 0 pin. standard serial i/o mode 2 adds four trans- mission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software commands of standard serial i/o mode 1. software commands are explained here below. table 1.183. software commands (standard serial i/o mode page read command control command 2nd byte 3rd byte 4th byte 5th byte 6th byte when id is not verified 1 page read ff 16 address (middle) address (high) data output data output data output data output to 259th byte not acceptable 2 page program 41 16 address (middle) address (high) data input data input data input data input to 259th byte not acceptable 3 block erase 20 16 address (middle) address (high) d0 16 not acceptable 4 erase all unlocked blocks a7 16 d0 16 not acceptable 5 read status register 70 16 srd output srd output acceptable 6 clear status register 50 16 not acceptable 7 read lock bit status 71 16 address (middle) address (high) lock bit data output not acceptable 8 lock bit program 77 16 address (middle) address (high) d0 16 not acceptable 9 lock bit enable 7a 16 not acceptable 10 lock bit disable 75 16 not acceptable 11 id check function f5 16 address (low) address (middle) address (high) id size id1 id7 acceptable 12 download function fa 16 size (low) size (high) check sum data input as required not acceptable 13 version data output function fb 16 version data output version data output version data output version data output version data output version data output to 9th byte acceptable 14 boot rom area output function fc 16 address (middle) address (high) data output data output data output data output to 259th byte not acceptable 15 read crc data fd 16 crc data (low) crc data (high) not acceptable 16 word read fe 16 address (low) address (middle) address (high) not acceptable 17 word program 40 16 address (low) address (middle) address (high) not acceptable 18 exit b9 16 acceptable 19 baud rate 9600 b0 16 b0 16 acceptable 20 baud rate 19200 b1 16 b1 16 acceptable note 1: the shaded areas indicate a transfer from flash mcu to serial programmer. all other data is transferred from programmer to mcu. note 2: srd to status register data. srd1 refers to status register 1 data. note 3: all commands are accepted if the reset vector is blank. 21 baud rate 38400 b2 16 b2 16 acceptable 22 baud rate 57600 b3 16 b3 16 acceptable
1-229 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (1) page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ?ff 16 ? command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 ?d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. figure 1.184. timing for page read data0 data255 rxd1 txd1 a 8 to a 15 a 16 to a 23 ff 16 (m16c receive data) (m16c transmit data) (2) page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) transfer the ?41 16 ? command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 ?d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. when the reception setup for the next 256 bytes ends, the rts1 (busy) signal changes from the "h" to the "l" level. the result of the page program is known by reading the status register. each block can be write protected with the lock bit. additional writing is not allowed with the pages programmed already. figure 1.185. timing for the page program rxd1 txd1 a 8 to a 15 a 16 to a 23 41 16 data0 data255 (m16c receive data) (m16c transmit data)
1-230 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (3) block erase command this command erases the data in the specified block. to execute the block erase command : (1) transfer the ?20 16 ? command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code ?d0 16 ? with the 4th byte. with the verify command code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 16 to a 23 . when block erase ends, the rts1 (busy) signal changes from the "h" to the "l" level. afterward, the result of the block erase operation is known by reading the status register. each block can be erase-protected with the lock bit. a 8 to a 15 a 16 to a 23 20 16 d0 16 rxd1 txd1 (m16c receive data) (m16c transmit data) (4) erase all unlocked blocks command this command erases the content of all blocks. execute the erase all blocks command as explained here following. (1) transfer the ?a7 16 ? command code with the 1st byte. (2) transfer the verify command code ?d0 16 ? with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. when block erasing ends, the rts1 (busy) signal changes from the "h" to the "l" level. the result of the erase operation is known be reading the status register. each block can be erase protected with the lock bit. figure 1.187. timing for erasing all unlocked blocks rxd1 txd1 a7 16 d0 16 (m16c transmit data) (m16c receive data) figure 1.188. timing for block erase
1-231 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (5) read status register command this command reads status information. when the ?70 16 ? command code is sent with the 1st byte, the con- tents of the status register (srd) specified with the 2nd byte and the contents of status register 1 (srd1) specified with the 3rd byte are read. (6) clear status register command this command clears the bits (sr3?sr5) which are set when the status register operation ends in error. when the ?50 16 ? command code is sent with the 1st byte, bits sr3-sr5 are cleared. when the clear status register operation ends, the rts1 (busy) signal changes from the "h" to the "l" level. figure 1.188. timing for reading the status register srd output srd1 output rxd1 txd1 70 16 (m16c receive data) (m16c transmit data) figure 1.189. timing for clearing the status register rxd1 txd1 50 16 (m16c receive data) (m16c transmit data) (7) read lock bit status command this command reads the lock bit status of the specified block. to execute the lock bit status command: (1) transfer the "71 16 " command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) the lock bit data of the specified block is output with the 4th byte. write the highest address of the speci- fied block for address a 8 to a 23 . figure 1.190. timing for lock bit status a 8 to a 15 a 16 to a 23 71 16 rxd1 txd1 (m16c transmit data) (m16c receive data) d0 16
1-232 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (8) lock bit program command this command writes "0" (lock) for the lock bit of the specified block. to execute the lock bit program com- mand : (1) transfer the "77 16 " command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes. (3) transfer the verify command code "d0 16 " with the 4th byte. with the verify command code, "0" is written for the lock bit of the specified block. write the highest address of the specified block for address a 8 to a 23 . when writing ends, rts1 (busy) signal changes from the "h" to "l". lock bit status can be read with the read lock bit status command. a 8 to a 15 a 16 to a 23 77 16 d0 16 rxd1 txd1 (m16c transmit data) (m16c receive data) figure 1.191. timing for the lock bit program (9) lock bit enable command this command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. the command code "7a 16 " is sent with the 1st byte of the serial transmission. this command only enables the lock bit function; it does not set the lock bit itself. rxd1 txd1 7a 16 (m16c receive data) (m16c transmit data) figure 1.192. timing for enabling the lock bit (10) lock bit disable command this command disables the lock bit. the command code "7516" is sent with the 1st byte of the serial transmis- sion. this command only disables the lock bit function; it does not set the lock bit itself. however, if an erase command is executed after executing the lock bit disable command, "0" (locked) lock bit data is set to "1" (unlocked) after the erase operation ends. in any case, after the reset is cancelled, the lock bit is enabled. rxd1 txd1 75 16 (m16c receive data) (m16c transmit data) figure 1.193. timing for disabling the lock bit
1-233 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (11) id check this command checks the id code. to execute the boot id check command: (1) transfer the ?f5 16 ? command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code with the 2nd, 3rd and 4th bytes respectively. (3) transfer the number of data sets of the id code with the 5th byte. (4) the id code is sent with the 6th byte onward, starting with the 1st byte of the code. figure 1.194. timing for the id check id size id1 id7 rxd1 txd1 f5 16 df 16 ff 16 0f 16 (m16c transmit data) (m16c receive data) id code when the flash memory is not blank, the id code sent from the peripheral units and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the peripheral units is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 and 0ffffb 16 . write a program into the flash memory, which already has the id code set for these addresses. figure 1.195. id code storage addresses reset watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0fffff 16 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address to
1-234 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (13) version information output command this command outputs the version information of the control program stored in the boot area. to execute the version information output command: (1) transfer the ?fb 16 ? command code with the 1st byte. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. (12) download command this command downloads a program to the ram for execution. to execute the download command: (1) transfer the ?fa 16 ? command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte on- ward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. figure 1.196. timing for download figure 1.197. timing for version information output fa 16 program data program data data size (high) data size (low) check sum rxd1 txd1 (m16c transmit data) (m16c receive data) fb 16 'x' 'v' 'e' 'r' rxd1 txd1 (m16c transmit data) (m16c receive data)
1-235 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (14) boot rom area output command this command outputs the control program stored in the boot rom area in one page blocks (256 bytes). to execute the boot rom area output command: (1) transfer the ?fc 16 ? command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 ?d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. figure 1.198. timing for boot rom area output data0 data255 rxd1 txd1 a 8 to a 15 a 16 to a 23 fc 16 ( m16c transmit data) (m16c receive data) (15) read crc data this command reads the crc data that confirms that the write data sent with the page program command was successfully received. (1) transfer the "fd 16 " command code with the 1st byte. (2) the crc data (low) is received with the 2nd byte and the crc data (high) with the 3rd byte. to use this command, first execute the command and then initialize the check data. next, execute the page program command the required number of times. after the read crc command is executed again, the crc data for all the read data that was sent with the page program command is read. the crc data is the result of crc operation of write data. rxd1 txd1 fd 16 (m16c receive data) (m16c transmit data) crc data (low) crc data (high) figure 1.199. timing for the read crc data
1-236 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (16) word read program this command reads the word from the specific address. to execute the word read command: (1) transfer the "fe 16 " command code with the 1st byte. (2) transfer the 3 byte address starting with the a0-a8 with the next 3 bytes. (3) the mcu transfers the byte at the specific address. (4) the mcu transfers the byte at the specific address +1. note: the specified address may be odd or even (a0=0 or 1) and be any value withing the 1m address space. low fe 16 rxd0 txd0 address address middle address high 1st half 2nd half of word of word figure 1.200. timing for word read program (17) word program this command writes the word in the flash memory. to execute the word program command: (1) transfer the "40 16 " with the 1st byte. (2) transfer the 3 byte address starting with the a0-a8 with the next 3 bytes. (3) transfer the 1st half of the word to be written in the lower address (a0=0). (4) transfer the 2nd half of the word to be written in the higher address (a0=1). note: the specified address must be even (a0=0). low 40 16 rxd0 txd0 address address middle address high 1st half 2nd half of word of word (18) exit command this command does a software reset by writing a "1" to bit 3 of the processor mode register 0. to execute the exit command: (1) transfer "b9 16 " with the 1st byte. (2) transfer the confirm command code "d0 16 " in the 2nd byte. if the cnvss line is low, the mcu will reset in normal mode and begin execution of the user code. if cnvss is high, the mcu will reset back into boot mode and begin execution at 7e000 16 again. figure 1.201. timing for word program rxd1 txd1 b9 16 d0 16 figure 1.202. timing for exit command
1-237 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (19) baud rate 9600 this command changes baud rate to 9,600 bps. to execute: (1) transfer the "b0 16 " command code with the 1st byte. (2) after the "b0 16 " check code is output with the 2nd byte, change the baud rate to 9,600 bps. figure 1.203. timing of baud rate 9600 (20) baud rate 19200 this command changes baud rate to 19,200 bps. execute it as follows. (1) transfer the "b1 16 " command code with the 1st byte. (2) after the "b1 16 " check code is output with the 2nd byte, change the baud rate to 19,200 bps. rxd1 txd1 b0 16 (m16c receive data) (m16c transmit data) b0 16 figure 1.204. timing of baud rate 19200 (21) baud rate 38400 this command changes baud rate to 38,400 bps. execute it as follows. (1) transfer the "b2 16 " command code with the 1st byte. (2) after the "b2 16 " check code is output with the 2nd byte, change the baud rate to 38,400 bps. figure 1.205. timing of baud rate 38400 rxd1 txd1 b1 16 (m16c receive data) (m16c transmit data) b1 16 rxd1 txd1 b2 16 (m16c receive data) (m16c transmit data) b2 16
1-238 under development specifications in this manual are tentative and subject to change rev. g serial i/o mode 2 (flash memory version) mitsubishi microcomputers M30222 group single-chip 16-bit cmos microcomputer (22) baud rate 57600 this command changes baud rate to 57,600 bps. execute it as follows. (1) transfer the "b3 16 " command code with the 1st byte. (2) after the "b3 16 " check code is output with the 2nd byte, change the baud rate to 57,600 bps. figure 1.206. timing of baud rate 57600 rxd1 txd1 b3 16 (m16c receive data) (m16c transmit data) b3 16 example circuit application for the standard serial i/o modes 1 and 2 figure 1.207 shows a circuit application for the standard serial i/o modes 1 and 2. control pins will vary according to programmer, therefore see the peripheral unit manual for more information. fig. 1.207. example circuit application for serial i/o modes 1 and 2 rts0(busy) clk0 r x d0 t x d0 cnvss clock input busy output data input data output m16c/ M30222 flash memory version (1) control pins and external circuitry will vary according to programmer. for more information, see the programmer manual. nmi cnvss reset reset

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